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author: Pacien TRAN-GIRARD 2014-04-11 19:29:53 +0200
committer: Pacien TRAN-GIRARD 2014-04-11 19:29:53 +0200
commit: 12bbdb42cdcf5e6e39832d75fbbd31e3781d550a (patch)
tree: 21d9d8fdb7a949c8050de38c237386d0066ca146 /FPGA/vhdl/lcd_message.vhd
download: fpga-home-automation-12bbdb42cdcf5e6e39832d75fbbd31e3781d550a.tar.gz
1 files changed, 158 insertions, 0 deletions
diff --git a/FPGA/vhdl/lcd_message.vhd b/FPGA/vhdl/lcd_message.vhd
new file mode 100644
index 0000000..7784055
--- /dev/null
+++ b/FPGA/vhdl/lcd_message.vhd
@@ -0,0 +1,158 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+entity lcd_message is 
+         
+        port( 
+        clk          : in std_logic;                      
+        resetn       : in  std_logic;      -- KEY0   
+        -- LCD signals
+        LCD_DATA   : inout std_logic_vector(7 downto 0); 
+        LCD_ON     : out std_logic;
+        LCD_BLON   : out std_logic;
+        LCD_RS     : out std_logic;               
+        LCD_RW     : out std_logic;               
+        LCD_EN     : out std_logic                 
+        );
+end entity;
+architecture RTL of lcd_message is
+   constant board_frequency : real := 50_000_000.0;
+        constant mode          : std_logic_vector(1 downto 0) := "00";
+        constant address       : std_logic_vector(6 downto 0):= "0000000";
+        constant char          : std_logic_vector(7 downto 0):= X"00";
+   constant write_char    : std_logic:='1';
+   constant write_address : std_logic:='1';
+   constant   go           : std_logic:='0';      
+        type state is (boot, message1,message2, waiting,write1,write2, reset1, reset2);
+        signal present    : state;
+        signal future     : state;    
+    signal lcd_write_char    : std_logic;
+    signal lcd_write_address : std_logic;
+    signal Din        : std_logic_vector (7 downto 0);
+    signal lcd_char   : std_logic_vector (7 downto 0);
+    signal lcd_ready  : std_logic;
+    signal cpt        : std_logic_vector(4 downto 0);
+    signal inc_cpt    : std_logic;
+ 
+    
+    signal lcd_mode   : std_logic_vector(1 downto 0);
+    signal lcd_address : std_logic_vector(address'range);
+    
+begin
+--------------------------------
+-- LCD
+--------------------------------
+  dut :   entity work.LCD
+    generic map (board_frequency => board_frequency)
+    port map( 
+        Clk         => clk,
+        resetn      => resetn,
+        
+        D             => '1',
+        C             => '0',
+        B             => '0',
+        
+        char          => lcd_char,
+        write_char    => lcd_write_char,
+        mode          => lcd_mode,
+        address       => lcd_address,
+        write_address => lcd_write_address,
+        ready         => lcd_ready,
+        LCD_ON        => LCD_ON,
+        LCD_BLON      => LCD_BLON,
+        LCD_data      => LCD_DATA,
+        Lcd_RS        => LCD_RS,
+        Lcd_RW        => LCD_RW,
+        Lcd_EN        => LCD_EN
+        );
+ 
+       
+        
+      
+     
+       
+  rom : entity work.message
+  port map (
+   adr => cpt,
+   do => din
+  );
+  
+       process(resetn,clk) is          
+       begin
+            if resetn = '0' then               
+              present <= boot;   
+              cpt     <= (others => '0');         
+            elsif rising_edge (clk) then                
+              present <= future;
+              if inc_cpt = '1' then cpt <= std_logic_vector(unsigned(cpt)+1);
+              end if;
+            end if;            
+       end process;
+  process(present, lcd_ready, cpt,Din ) is
+  begin
+    future     <= present;
+    inc_cpt    <= '0'; 
+    
+    lcd_write_char    <= '0';
+    lcd_write_address <= '0';
+    lcd_char          <= char;
+    lcd_mode          <= mode;
+    lcd_address       <= address;
+    
+    case present is 
+      when boot   => if lcd_ready = '1' then future <= reset1; 
+                     end if;
+                     lcd_mode <= "00";
+                     
+                     
+      when waiting    => future <= waiting;                     
+     
+     when reset1  => lcd_write_char    <= '1';
+                     lcd_write_address <= '0';
+                     lcd_char          <= X"0C";  
+                     lcd_address       <= "0000000";   
+                     lcd_mode          <= "00";           
+                     if lcd_ready = '0' then future <= reset2;     
+                     end if;  
+                     
+     when reset2  => if lcd_ready = '1' then future <= message1;     
+                     end if;       
+                     
+                     
+     when message1 => if lcd_ready = '0' then future <= message2; 
+                     end if;
+                     lcd_write_char <= '1';
+                     lcd_mode       <= "00";
+                     lcd_char       <= Din;
+                     
+     when message2 => if lcd_ready = '1' then 
+                        if unsigned (cpt) <31 then future <= message1; 
+                        else future <= waiting;
+                        end if;
+                        inc_cpt <= '1';
+                     end if;
+                     lcd_mode <= "00";
+                     lcd_char <= Din;
+      
+     when write1  =>  lcd_write_char    <= not write_char;
+                      lcd_write_address <= not write_address;
+                      lcd_char          <= char;                      
+                     if lcd_ready = '0' then future <= write2;   
+                     end if;  
+                                 
+     when write2  => if  write_char= '1' and write_address = '1' and lcd_ready= '1' then
+                      future <= waiting ;
+                     end if; 
+                     
+                                
+    end case;
+  end process; 
+end architecture;
+    
+\ No newline at end of file
author	Pacien TRAN-GIRARD	2014-04-11 19:29:53 +0200
committer	Pacien TRAN-GIRARD	2014-04-11 19:29:53 +0200
commit	12bbdb42cdcf5e6e39832d75fbbd31e3781d550a (patch)
tree	21d9d8fdb7a949c8050de38c237386d0066ca146 /FPGA/vhdl/lcd_message.vhd
download	fpga-home-automation-12bbdb42cdcf5e6e39832d75fbbd31e3781d550a.tar.gz

diff --git a/FPGA/vhdl/lcd_message.vhd b/FPGA/vhdl/lcd_message.vhd new file mode 100644 index 0000000..7784055 --- /dev/null +++ b/FPGA/vhdl/lcd_message.vhd
@@ -0,0 +1,158 @@
	1	library ieee;
	2	use ieee.std_logic_1164.all;
	3	use ieee.numeric_std.all;
	4
	5	entity lcd_message is
	6
	7	port(
	8	clk : in std_logic;
	9	resetn : in std_logic; -- KEY0
	10	-- LCD signals
	11	LCD_DATA : inout std_logic_vector(7 downto 0);
	12	LCD_ON : out std_logic;
	13	LCD_BLON : out std_logic;
	14	LCD_RS : out std_logic;
	15	LCD_RW : out std_logic;
	16	LCD_EN : out std_logic
	17	);
	18	end entity;
	19
	20	architecture RTL of lcd_message is
	21	constant board_frequency : real := 50_000_000.0;
	22	constant mode : std_logic_vector(1 downto 0) := "00";
	23	constant address : std_logic_vector(6 downto 0):= "0000000";
	24	constant char : std_logic_vector(7 downto 0):= X"00";
	25	constant write_char : std_logic:='1';
	26	constant write_address : std_logic:='1';
	27	constant go : std_logic:='0';
	28	type state is (boot, message1,message2, waiting,write1,write2, reset1, reset2);
	29	signal present : state;
	30	signal future : state;
	31
	32	signal lcd_write_char : std_logic;
	33	signal lcd_write_address : std_logic;
	34	signal Din : std_logic_vector (7 downto 0);
	35	signal lcd_char : std_logic_vector (7 downto 0);
	36	signal lcd_ready : std_logic;
	37	signal cpt : std_logic_vector(4 downto 0);
	38	signal inc_cpt : std_logic;
	39
	40
	41	signal lcd_mode : std_logic_vector(1 downto 0);
	42	signal lcd_address : std_logic_vector(address'range);
	43
	44	begin
	45
	46
	47	--------------------------------
	48	-- LCD
	49	--------------------------------
	50
	51	dut : entity work.LCD
	52	generic map (board_frequency => board_frequency)
	53	port map(
	54	Clk => clk,
	55	resetn => resetn,
	56
	57	D => '1',
	58	C => '0',
	59	B => '0',
	60
	61	char => lcd_char,
	62	write_char => lcd_write_char,
	63	mode => lcd_mode,
	64	address => lcd_address,
	65	write_address => lcd_write_address,
	66	ready => lcd_ready,
	67	LCD_ON => LCD_ON,
	68	LCD_BLON => LCD_BLON,
	69	LCD_data => LCD_DATA,
	70	Lcd_RS => LCD_RS,
	71	Lcd_RW => LCD_RW,
	72	Lcd_EN => LCD_EN
	73	);
	74
	75
	76
	77
	78
	79
	80	rom : entity work.message
	81	port map (
	82	adr => cpt,
	83	do => din
	84	);
	85
	86	process(resetn,clk) is
	87	begin
	88	if resetn = '0' then
	89	present <= boot;
	90	cpt <= (others => '0');
	91	elsif rising_edge (clk) then
	92	present <= future;
	93	if inc_cpt = '1' then cpt <= std_logic_vector(unsigned(cpt)+1);
	94	end if;
	95	end if;
	96	end process;
	97
	98	process(present, lcd_ready, cpt,Din ) is
	99	begin
	100	future <= present;
	101	inc_cpt <= '0';
	102
	103	lcd_write_char <= '0';
	104	lcd_write_address <= '0';
	105	lcd_char <= char;
	106	lcd_mode <= mode;
	107	lcd_address <= address;
	108
	109	case present is
	110	when boot => if lcd_ready = '1' then future <= reset1;
	111	end if;
	112	lcd_mode <= "00";
	113
	114
	115	when waiting => future <= waiting;
	116
	117	when reset1 => lcd_write_char <= '1';
	118	lcd_write_address <= '0';
	119	lcd_char <= X"0C";
	120	lcd_address <= "0000000";
	121	lcd_mode <= "00";
	122	if lcd_ready = '0' then future <= reset2;
	123	end if;
	124
	125	when reset2 => if lcd_ready = '1' then future <= message1;
	126	end if;
	127
	128
	129	when message1 => if lcd_ready = '0' then future <= message2;
	130	end if;
	131	lcd_write_char <= '1';
	132	lcd_mode <= "00";
	133	lcd_char <= Din;
	134
	135	when message2 => if lcd_ready = '1' then
	136	if unsigned (cpt) <31 then future <= message1;
	137	else future <= waiting;
	138	end if;
	139	inc_cpt <= '1';
	140	end if;
	141	lcd_mode <= "00";
	142	lcd_char <= Din;
	143
	144	when write1 => lcd_write_char <= not write_char;
	145	lcd_write_address <= not write_address;
	146	lcd_char <= char;
	147	if lcd_ready = '0' then future <= write2;
	148	end if;
	149
	150	when write2 => if write_char= '1' and write_address = '1' and lcd_ready= '1' then
	151	future <= waiting ;
	152	end if;
	153
	154
	155	end case;
	156	end process;
	157	end architecture;
	158	\ No newline at end of file