Import fichiers projet Quartus

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diff --git a/FPGA/vhdl/rom_sinus.vhd b/FPGA/vhdl/rom_sinus.vhd
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+----------------------------------------------------
+--        QUART de SINUS : SYNCHRONOUS ROM
+----------------------------------------------------
+-- ESIEE
+-- creation     : A. Exertier, 06/2009
+-- modification : A. Exertier, 12/2011
+----------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+-----------------------------------------------------
+--                GENERIC PARAMETER
+-----------------------------------------------------
+-- N_data         : output data number of bits
+-- N_adr_ROM      : address number of bits
+-- amplitude      : sinus amplitude 
+--                  should be < 2**N_data
+-----------------------------------------------------
+--                INPUTS
+-----------------------------------------------------
+-- clk            : clock
+-- address        : ROM address
+-----------------------------------------------------
+--                OUTPUT
+-----------------------------------------------------
+-- data           : output data
+-----------------------------------------------------
+
+entity rom_sinus is 
+  generic ( 
+  N_data    : natural := 14;
+  N_adr_ROM : natural := 8;
+  amplitude : natural := 1024
+  );
+  port (
+  clk     : in  std_logic;
+  address : in  std_logic_vector(N_adr_ROM-1 downto 0);
+  data    : out std_logic_vector(N_data-2 downto 0));   
+  
+end entity rom_sinus;       
+
+architecture RTL of rom_sinus is
+  subtype DAC_data_type   is std_logic_vector (N_data-2 downto 0);
+  type memory_type is array (0 to 2**N_adr_ROM-1) of DAC_data_type;
+  
+ function sinus_tabule  return memory_type is
+  variable temp : memory_type;
+  variable sinus_real : real;
+ begin
+  for i in 0 to 2**N_adr_ROM-1 loop
+      sinus_real := real(amplitude)*(sin(math_pi_over_2 * real(i)/real(2**N_adr_ROM)));
+      if integer(sinus_real)= 2**(N_data-1) then
+        temp(i) := (others => '1');
+      else
+      temp(i) := std_logic_vector(to_unsigned(integer(sinus_real), N_data-1));
+      end if;
+  end loop; 
+  return temp;
+ end sinus_tabule;     
+  
+  constant memory_values : memory_type := sinus_tabule;
+
+begin 
+   
+    process(clk) is
+     begin 
+       if rising_edge(clk) then data<= memory_values(to_integer(unsigned(address)));           
+       end if;
+   end process;
+        
+end RTL;