1 files changed, 146 insertions, 0 deletions

diff --git a/FPGA/display/lpm_shiftreg0.vhd b/FPGA/display/lpm_shiftreg0.vhd
new file mode 100644
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+++ b/FPGA/display/lpm_shiftreg0.vhd
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+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: LPM_SHIFTREG 
+
+-- ============================================================
+-- File Name: lpm_shiftreg0.vhd
+-- Megafunction Name(s):
+--                      LPM_SHIFTREG
+--
+-- Simulation Library Files(s):
+--                      lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg0 IS
+        PORT
+        (
+                aset            : IN STD_LOGIC ;
+                clock           : IN STD_LOGIC ;
+                enable          : IN STD_LOGIC ;
+                shiftin         : IN STD_LOGIC ;
+                q               : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+                shiftout                : OUT STD_LOGIC 
+        );
+END lpm_shiftreg0;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg0 IS
+
+        SIGNAL sub_wire0        : STD_LOGIC ;
+        SIGNAL sub_wire1        : STD_LOGIC_VECTOR (11 DOWNTO 0);
+
+
+
+        COMPONENT lpm_shiftreg
+        GENERIC (
+                lpm_avalue              : STRING;
+                lpm_direction           : STRING;
+                lpm_type                : STRING;
+                lpm_width               : NATURAL
+        );
+        PORT (
+                        clock   : IN STD_LOGIC ;
+                        shiftout        : OUT STD_LOGIC ;
+                        aset    : IN STD_LOGIC ;
+                        enable  : IN STD_LOGIC ;
+                        q       : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
+                        shiftin : IN STD_LOGIC 
+        );
+        END COMPONENT;
+
+BEGIN
+        shiftout    <= sub_wire0;
+        q    <= sub_wire1(11 DOWNTO 0);
+
+        LPM_SHIFTREG_component : LPM_SHIFTREG
+        GENERIC MAP (
+                lpm_avalue => "2080",
+                lpm_direction => "LEFT",
+                lpm_type => "LPM_SHIFTREG",
+                lpm_width => 12
+        )
+        PORT MAP (
+                clock => clock,
+                aset => aset,
+                enable => enable,
+                shiftin => shiftin,
+                shiftout => sub_wire0,
+                q => sub_wire1
+        );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "1"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "0"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "12"
+-- Retrieval info: PRIVATE: new_diagram STRING "1"
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: CONSTANT: LPM_AVALUE STRING "2080"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
+-- Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL "aset"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL "enable"
+-- Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL "shiftin"
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL "shiftout"
+-- Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm