From 693a38c41f26c27e54a7e8b96c550eaf6008b56f Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Fri, 11 Apr 2014 22:37:38 +0200 Subject: Add display module --- FPGA/display/display.bdf | 503 +++++++++++++++++++++++++++++++++ FPGA/display/display.qpf | 30 ++ FPGA/display/display.qsf | 118 ++++++++ FPGA/display/display_pin.tcl | 62 ++++ FPGA/display/lpm_constant_1.bsf | 49 ++++ FPGA/display/lpm_constant_1.cmp | 21 ++ FPGA/display/lpm_constant_1.vhd | 109 +++++++ FPGA/display/lpm_constant_a.bsf | 49 ++++ FPGA/display/lpm_constant_a.cmp | 21 ++ FPGA/display/lpm_constant_a.vhd | 109 +++++++ FPGA/display/lpm_constant_f.bsf | 49 ++++ FPGA/display/lpm_constant_f.cmp | 21 ++ FPGA/display/lpm_constant_f.vhd | 109 +++++++ FPGA/display/seven_segment_decoder.bsf | 49 ++++ 14 files changed, 1299 insertions(+) create mode 100644 FPGA/display/display.bdf create mode 100644 FPGA/display/display.qpf create mode 100644 FPGA/display/display.qsf create mode 100644 FPGA/display/display_pin.tcl create mode 100644 FPGA/display/lpm_constant_1.bsf create mode 100644 FPGA/display/lpm_constant_1.cmp create mode 100644 FPGA/display/lpm_constant_1.vhd create mode 100644 FPGA/display/lpm_constant_a.bsf create mode 100644 FPGA/display/lpm_constant_a.cmp create mode 100644 FPGA/display/lpm_constant_a.vhd create mode 100644 FPGA/display/lpm_constant_f.bsf create mode 100644 FPGA/display/lpm_constant_f.cmp create mode 100644 FPGA/display/lpm_constant_f.vhd create mode 100644 FPGA/display/seven_segment_decoder.bsf diff --git a/FPGA/display/display.bdf b/FPGA/display/display.bdf new file mode 100644 index 0000000..c40e75b --- /dev/null +++ b/FPGA/display/display.bdf @@ -0,0 +1,503 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 96 48 272 64) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "fan_auto" (rect 9 0 52 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 96 64 272 80) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "alarm_user" (rect 9 0 65 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 96 80 272 96) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "speed[1..0]" (rect 9 0 64 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 760 48 936 64) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hex7[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 760 64 936 80) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hex6[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line 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8)(pt 24 8)) + ) +) +(symbol + (rect 392 496 568 576) + (text "seven_segment_decoder" (rect 5 0 130 11)(font "Arial" )) + (text "fan_speed" (rect 8 64 59 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "hexa[3..0]" (rect 0 0 48 11)(font "Arial" )) + (text "hexa[3..0]" (rect 21 27 69 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "hex[6..0]" (rect 0 0 42 11)(font "Arial" )) + (text "hex[6..0]" (rect 120 27 155 38)(font "Arial" )) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (parameter + "active_low" + "true" + "" + (type "PARAMETER_ENUM") ) + (drawing + (rectangle (rect 16 16 160 64)) + ) + (annotation_block (parameter)(rect 568 464 728 496)) +) +(symbol + (rect 392 624 568 704) + (text "seven_segment_decoder" (rect 5 0 130 11)(font "Arial" )) + (text "a" (rect 8 64 15 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "hexa[3..0]" (rect 0 0 48 11)(font "Arial" )) + (text "hexa[3..0]" (rect 21 27 69 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+ (pt 568 784) + (pt 584 784) + (bus) +) +(connector + (text "alarm_user" (rect 464 408 475 464)(font "Arial" )(vertical)) + (pt 480 408) + (pt 480 472) +) +(connector + (text "fan_auto" (rect 464 243 475 286)(font "Arial" )(vertical)) + (pt 480 240) + (pt 480 296) +) +(connector + (text "speed[3..0]" (rect 320 520 375 531)(font "Arial" )) + (pt 376 528) + (pt 392 528) + (bus) +) +(connector + (text "hex_f[6..0]" (rect 368 200 419 211)(font "Arial" )) + (pt 360 216) + (pt 424 216) + (bus) +) +(connector + (text "nada[6..0]" (rect 368 168 417 179)(font "Arial" )) + (pt 360 184) + (pt 424 184) + (bus) +) +(connector + (text "hex_a[6..0]" (rect 368 368 423 379)(font "Arial" )) + (pt 360 384) + (pt 424 384) + (bus) +) +(connector + (text "nada[6..0]" (rect 368 336 417 347)(font "Arial" )) + (pt 360 352) + (pt 424 352) + (bus) +) +(connector + (text "hex_a[6..0]" (rect 577 640 632 651)(font "Arial" )) + (pt 568 656) + (pt 584 656) + (bus) +) +(connector + (text "hex6[6..0]" (rect 544 184 592 195)(font "Arial" )) + (pt 536 200) + (pt 552 200) + (bus) +) +(connector + (text "hex7[6..0]" (rect 544 352 592 363)(font "Arial" )) + (pt 536 368) + (pt 552 368) + (bus) +) +(connector + (pt 392 784) + (pt 376 784) + (bus) +) +(connector + (pt 376 656) + (pt 392 656) + (bus) +) +(connector + (text "nada[6..0]" (rect 544 56 593 67)(font "Arial" )) + (pt 552 72) + (pt 536 72) + (bus) +) +(connector + (pt 232 512) + (pt 232 528) +) +(connector + (pt 232 528) + (pt 232 544) +) +(junction (pt 232 528)) diff --git a/FPGA/display/display.qpf b/FPGA/display/display.qpf new file mode 100644 index 0000000..c0db20c --- /dev/null +++ b/FPGA/display/display.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 21:12:46 April 11, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "21:12:46 April 11, 2014" + +# Revisions + +PROJECT_REVISION = "display" diff --git a/FPGA/display/display.qsf b/FPGA/display/display.qsf new file mode 100644 index 0000000..4a3d072 --- /dev/null +++ b/FPGA/display/display.qsf @@ -0,0 +1,118 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 21:12:46 April 11, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# display_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY display +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:12:46 APRIL 11, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" +set_location_assignment PIN_AE14 -to speed[1] +set_location_assignment PIN_P25 -to speed[0] +set_location_assignment PIN_N26 -to fan_auto +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] +set_global_assignment -name BDF_FILE display.bdf +set_global_assignment -name VHDL_FILE ../vhdl/seven_segment_decoder.vhd +set_global_assignment -name TCL_SCRIPT_FILE display_pin.tcl +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA/display/display_pin.tcl b/FPGA/display/display_pin.tcl new file mode 100644 index 0000000..79fc8ad --- /dev/null +++ b/FPGA/display/display_pin.tcl @@ -0,0 +1,62 @@ +set_location_assignment PIN_AE14 -to speed[1] +set_location_assignment PIN_P25 -to speed[0] + +set_location_assignment PIN_N26 -to fan_auto +set_location_assignment PIN_N25 -to alarm_user + +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] \ No newline at end of file diff --git a/FPGA/display/lpm_constant_1.bsf b/FPGA/display/lpm_constant_1.bsf new file mode 100644 index 0000000..9fa56d2 --- /dev/null +++ b/FPGA/display/lpm_constant_1.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 112 48) + (text "lpm_constant_1" (rect 10 0 120 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 33 25 44)(font "Arial" )) + (port + (pt 112 24) + (output) + (text "result[6..0]" (rect 0 0 58 13)(font "Arial" (font_size 8))) + (text "127" (rect 75 18 91 30)(font "Arial" (font_size 8))) + (line (pt 112 24)(pt 96 24)(line_width 3)) + ) + (drawing + (text "7" (rect 99 27 202 64)(font "Arial" )) + (line (pt 106 20)(pt 98 28)) + (line (pt 16 16)(pt 16 32)) + (line (pt 16 16)(pt 96 16)) + (line (pt 16 32)(pt 96 32)) + (line (pt 96 16)(pt 96 32)) + (line (pt 0 0)(pt 114 0)) + (line (pt 114 0)(pt 114 50)) + (line (pt 0 50)(pt 114 50)) + (line (pt 0 0)(pt 0 50)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/FPGA/display/lpm_constant_1.cmp b/FPGA/display/lpm_constant_1.cmp new file mode 100644 index 0000000..bf06257 --- /dev/null +++ b/FPGA/display/lpm_constant_1.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant_1 + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/FPGA/display/lpm_constant_1.vhd b/FPGA/display/lpm_constant_1.vhd new file mode 100644 index 0000000..e335a61 --- /dev/null +++ b/FPGA/display/lpm_constant_1.vhd @@ -0,0 +1,109 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_CONSTANT + +-- ============================================================ +-- File Name: lpm_constant_1.vhd +-- Megafunction Name(s): +-- LPM_CONSTANT +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant_1 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_constant_1; + + +ARCHITECTURE SYN OF lpm_constant_1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(6 DOWNTO 0); + + LPM_CONSTANT_component : LPM_CONSTANT + GENERIC MAP ( + lpm_cvalue => 127, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 7 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "127" +-- Retrieval info: PRIVATE: nBit NUMERIC "7" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "127" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]" +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA/display/lpm_constant_a.bsf b/FPGA/display/lpm_constant_a.bsf new file mode 100644 index 0000000..068564f --- /dev/null +++ b/FPGA/display/lpm_constant_a.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 112 48) + (text "lpm_constant_a" (rect 10 0 120 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 33 25 44)(font "Arial" )) + (port + (pt 112 24) + (output) + (text "result[3..0]" (rect 0 0 58 13)(font "Arial" (font_size 8))) + (text "10" (rect 81 18 91 30)(font "Arial" (font_size 8))) + (line (pt 112 24)(pt 96 24)(line_width 3)) + ) + (drawing + (text "4" (rect 99 27 202 64)(font "Arial" )) + (line (pt 106 20)(pt 98 28)) + (line (pt 16 16)(pt 16 32)) + (line (pt 16 16)(pt 96 16)) + (line (pt 16 32)(pt 96 32)) + (line (pt 96 16)(pt 96 32)) + (line (pt 0 0)(pt 114 0)) + (line (pt 114 0)(pt 114 50)) + (line (pt 0 50)(pt 114 50)) + (line (pt 0 0)(pt 0 50)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/FPGA/display/lpm_constant_a.cmp b/FPGA/display/lpm_constant_a.cmp new file mode 100644 index 0000000..38e33e2 --- /dev/null +++ b/FPGA/display/lpm_constant_a.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant_a + PORT + ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA/display/lpm_constant_a.vhd b/FPGA/display/lpm_constant_a.vhd new file mode 100644 index 0000000..85be988 --- /dev/null +++ b/FPGA/display/lpm_constant_a.vhd @@ -0,0 +1,109 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_CONSTANT + +-- ============================================================ +-- File Name: lpm_constant_a.vhd +-- Megafunction Name(s): +-- LPM_CONSTANT +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant_a IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END lpm_constant_a; + + +ARCHITECTURE SYN OF lpm_constant_a IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(3 DOWNTO 0); + + LPM_CONSTANT_component : LPM_CONSTANT + GENERIC MAP ( + lpm_cvalue => 10, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 4 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "16" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "10" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "10" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]" +-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_a.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_a.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_a.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_a.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_a_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA/display/lpm_constant_f.bsf b/FPGA/display/lpm_constant_f.bsf new file mode 100644 index 0000000..2040994 --- /dev/null +++ b/FPGA/display/lpm_constant_f.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 112 48) + (text "lpm_constant_f" (rect 12 0 120 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 33 25 44)(font "Arial" )) + (port + (pt 112 24) + (output) + (text "result[3..0]" (rect 0 0 58 13)(font "Arial" (font_size 8))) + (text "15" (rect 81 18 91 30)(font "Arial" (font_size 8))) + (line (pt 112 24)(pt 96 24)(line_width 3)) + ) + (drawing + (text "4" (rect 99 27 202 64)(font "Arial" )) + (line (pt 106 20)(pt 98 28)) + (line (pt 16 16)(pt 16 32)) + (line (pt 16 16)(pt 96 16)) + (line (pt 16 32)(pt 96 32)) + (line (pt 96 16)(pt 96 32)) + (line (pt 0 0)(pt 114 0)) + (line (pt 114 0)(pt 114 50)) + (line (pt 0 50)(pt 114 50)) + (line (pt 0 0)(pt 0 50)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/FPGA/display/lpm_constant_f.cmp b/FPGA/display/lpm_constant_f.cmp new file mode 100644 index 0000000..6d64867 --- /dev/null +++ b/FPGA/display/lpm_constant_f.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant_f + PORT + ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA/display/lpm_constant_f.vhd b/FPGA/display/lpm_constant_f.vhd new file mode 100644 index 0000000..f9e0f69 --- /dev/null +++ b/FPGA/display/lpm_constant_f.vhd @@ -0,0 +1,109 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_CONSTANT + +-- ============================================================ +-- File Name: lpm_constant_f.vhd +-- Megafunction Name(s): +-- LPM_CONSTANT +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant_f IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END lpm_constant_f; + + +ARCHITECTURE SYN OF lpm_constant_f IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(3 DOWNTO 0); + + LPM_CONSTANT_component : LPM_CONSTANT + GENERIC MAP ( + lpm_cvalue => 15, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 4 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "16" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "15" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "15" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]" +-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_f.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_f.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_f.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_f.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant_f_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA/display/seven_segment_decoder.bsf b/FPGA/display/seven_segment_decoder.bsf new file mode 100644 index 0000000..2b2db67 --- /dev/null +++ b/FPGA/display/seven_segment_decoder.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 192 96) + (text "seven_segment_decoder" (rect 5 0 107 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "hexa[3..0]" (rect 0 0 38 12)(font "Arial" )) + (text "hexa[3..0]" (rect 21 27 59 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "hex[6..0]" (rect 0 0 34 12)(font "Arial" )) + (text "hex[6..0]" (rect 121 27 155 39)(font "Arial" )) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (parameter + "active_low" + "true" + "" + (type "PARAMETER_ENUM") ) + (drawing + (rectangle (rect 16 16 160 64)(line_width 1)) + ) + (annotation_block (parameter)(rect 192 -64 292 16)) +) -- cgit v1.2.3