From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Fri, 13 Jun 2014 16:06:19 +0200 Subject: Update project --- FPGA/codec_clock/clock_divider.bsf | 61 ++++++++++++++++++++ FPGA/codec_clock/codec_clock.bdf | 112 +++++++++++++++++++++++++++++++++++++ FPGA/codec_clock/codec_clock.bsf | 50 +++++++++++++++++ FPGA/codec_clock/codec_clock.qpf | 30 ++++++++++ FPGA/codec_clock/codec_clock.qsf | 78 ++++++++++++++++++++++++++ FPGA/codec_clock/codec_clock.qws | Bin 0 -> 2276 bytes 6 files changed, 331 insertions(+) create mode 100644 FPGA/codec_clock/clock_divider.bsf create mode 100644 FPGA/codec_clock/codec_clock.bdf create mode 100644 FPGA/codec_clock/codec_clock.bsf create mode 100644 FPGA/codec_clock/codec_clock.qpf create mode 100644 FPGA/codec_clock/codec_clock.qsf create mode 100644 FPGA/codec_clock/codec_clock.qws (limited to 'FPGA/codec_clock') diff --git a/FPGA/codec_clock/clock_divider.bsf b/FPGA/codec_clock/clock_divider.bsf new file mode 100644 index 0000000..de8cb37 --- /dev/null +++ b/FPGA/codec_clock/clock_divider.bsf @@ -0,0 +1,61 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 96) + (text "clock_divider" (rect 5 0 56 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "en_user" (rect 0 0 33 12)(font "Arial" )) + (text "en_user" (rect 106 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 1)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (parameter + "user_frequency" + "4.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 144 64)(line_width 1)) + ) + (annotation_block (parameter)(rect 176 -64 276 16)) +) diff --git a/FPGA/codec_clock/codec_clock.bdf b/FPGA/codec_clock/codec_clock.bdf new file mode 100644 index 0000000..df9857d --- /dev/null +++ b/FPGA/codec_clock/codec_clock.bdf @@ -0,0 +1,112 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 128 104 296 120) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 21 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 72 120 128 136)) +) +(pin + (input) + (rect 128 120 296 136) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "resetn" (rect 5 0 37 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 64 136 128 152)) +) +(pin + (output) + (rect 456 104 632 120) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "xti_mclk" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 632 120 696 136)) +) +(symbol + (rect 296 80 456 160) + (text "clock_divider" (rect 5 0 71 11)(font "Arial" )) + (text "inst" (rect 8 64 26 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 15 11)(font "Arial" )) + (text "clk" (rect 21 27 36 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 31 11)(font "Arial" )) + (text "resetn" (rect 21 43 52 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 160 32) + (output) + (text "en_user" (rect 0 0 42 11)(font "Arial" )) + (text "en_user" (rect 104 27 146 38)(font "Arial" )) + (line (pt 160 32)(pt 144 32)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (parameter + "user_frequency" + "16666666.6" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 144 64)) + ) + (annotation_block (parameter)(rect 456 40 641 79)) +) diff --git a/FPGA/codec_clock/codec_clock.bsf b/FPGA/codec_clock/codec_clock.bsf new file mode 100644 index 0000000..c112470 --- /dev/null +++ b/FPGA/codec_clock/codec_clock.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 152 112) + (text "codec_clock" (rect 5 0 76 13)(font "Arial" (font_size 8))) + (text "inst" (rect 8 81 26 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8))) + (text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 136 32) + (output) + (text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8))) + (text "xti_mclk" (rect 67 27 115 40)(font "Arial" (font_size 8))) + (line (pt 136 32)(pt 120 32)) + ) + (drawing + (rectangle (rect 16 16 120 80)) + ) +) diff --git a/FPGA/codec_clock/codec_clock.qpf b/FPGA/codec_clock/codec_clock.qpf new file mode 100644 index 0000000..0dac0d9 --- /dev/null +++ b/FPGA/codec_clock/codec_clock.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:18:56 mai 26, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:18:56 mai 26, 2014" + +# Revisions + +PROJECT_REVISION = "codec_clock" diff --git a/FPGA/codec_clock/codec_clock.qsf b/FPGA/codec_clock/codec_clock.qsf new file mode 100644 index 0000000..c11cd5a --- /dev/null +++ b/FPGA/codec_clock/codec_clock.qsf @@ -0,0 +1,78 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:18:56 mai 26, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# codec_clock_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY codec_clock +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:18:56 MAI 26, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd +set_global_assignment -name BDF_FILE codec_clock.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_AE23 -to alarm +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_M23 -to hot +set_location_assignment PIN_K26 -to fan +set_location_assignment PIN_B4 -to aud_bclk +set_location_assignment PIN_A4 -to aud_dacdat +set_location_assignment PIN_C6 -to aud_daclrck +set_location_assignment PIN_A5 -to aud_xck +set_location_assignment PIN_A6 -to i2c_sclk +set_location_assignment PIN_B6 -to i2c_sdat +set_location_assignment PIN_M20 -to sound_high_level +set_location_assignment PIN_Y18 -to led_fan +set_location_assignment PIN_AE22 -to end_config +set_location_assignment PIN_M25 -to xti_mclk +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA/codec_clock/codec_clock.qws b/FPGA/codec_clock/codec_clock.qws new file mode 100644 index 0000000..b64e61b Binary files /dev/null and b/FPGA/codec_clock/codec_clock.qws differ -- cgit v1.2.3