From 4762ef9b7238f67d065775b752ebf51289c1f437 Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Sun, 15 Jun 2014 15:28:10 +0200
Subject: Clean project

---
 FPGA/pwm/greybox_tmp/cbx_args.txt        |  7 -----
 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v | 52 --------------------------------
 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v | 51 -------------------------------
 3 files changed, 110 deletions(-)
 delete mode 100644 FPGA/pwm/greybox_tmp/cbx_args.txt
 delete mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
 delete mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v

(limited to 'FPGA/pwm/greybox_tmp')

diff --git a/FPGA/pwm/greybox_tmp/cbx_args.txt b/FPGA/pwm/greybox_tmp/cbx_args.txt
deleted file mode 100644
index 662f251..0000000
--- a/FPGA/pwm/greybox_tmp/cbx_args.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-LPM_REPRESENTATION=UNSIGNED
-LPM_TYPE=LPM_COMPARE
-LPM_WIDTH=23
-DEVICE_FAMILY="Cyclone II"
-dataa
-datab
-alb
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
deleted file mode 100644
index 90c1893..0000000
--- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
+++ /dev/null
@@ -1,52 +0,0 @@
-//lpm_mux CBX_SINGLE_OUTPUT_FILE="ON" LPM_SIZE=4 LPM_TYPE="LPM_MUX" LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
-//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 1991-2013 Altera Corporation
-//  Your use of Altera Corporation's design tools, logic functions 
-//  and other software and tools, and its AMPP partner logic 
-//  functions, and any output files from any of the foregoing 
-//  (including device programming or simulation files), and any 
-//  associated documentation or information are expressly subject 
-//  to the terms and conditions of the Altera Program License 
-//  Subscription Agreement, Altera MegaCore Function License 
-//  Agreement, or other applicable license agreement, including, 
-//  without limitation, that your use is for the sole purpose of 
-//  programming logic devices manufactured by Altera and sold by 
-//  Altera or its authorized distributors.  Please refer to the 
-//  applicable agreement for further details.
-
-
-
-//synthesis_resources = lpm_mux 1 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  mgbt9
-	( 
-	data,
-	result,
-	sel) /* synthesis synthesis_clearbox=1 */;
-	input   [3:0]  data;
-	output   [0:0]  result;
-	input   [1:0]  sel;
-
-	wire  [0:0]   wire_mgl_prim1_result;
-
-	lpm_mux   mgl_prim1
-	( 
-	.data(data),
-	.result(wire_mgl_prim1_result),
-	.sel(sel));
-	defparam
-		mgl_prim1.lpm_size = 4,
-		mgl_prim1.lpm_type = "LPM_MUX",
-		mgl_prim1.lpm_width = 1,
-		mgl_prim1.lpm_widths = 2;
-	assign
-		result = wire_mgl_prim1_result;
-endmodule //mgbt9
-//VALID FILE
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
deleted file mode 100644
index 8fab5c3..0000000
--- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
+++ /dev/null
@@ -1,51 +0,0 @@
-//lpm_compare CBX_SINGLE_OUTPUT_FILE="ON" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_COMPARE" LPM_WIDTH=23 alb dataa datab
-//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 1991-2013 Altera Corporation
-//  Your use of Altera Corporation's design tools, logic functions 
-//  and other software and tools, and its AMPP partner logic 
-//  functions, and any output files from any of the foregoing 
-//  (including device programming or simulation files), and any 
-//  associated documentation or information are expressly subject 
-//  to the terms and conditions of the Altera Program License 
-//  Subscription Agreement, Altera MegaCore Function License 
-//  Agreement, or other applicable license agreement, including, 
-//  without limitation, that your use is for the sole purpose of 
-//  programming logic devices manufactured by Altera and sold by 
-//  Altera or its authorized distributors.  Please refer to the 
-//  applicable agreement for further details.
-
-
-
-//synthesis_resources = lpm_compare 1 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  mgtbb
-	( 
-	alb,
-	dataa,
-	datab) /* synthesis synthesis_clearbox=1 */;
-	output   alb;
-	input   [22:0]  dataa;
-	input   [22:0]  datab;
-
-	wire  wire_mgl_prim1_alb;
-
-	lpm_compare   mgl_prim1
-	( 
-	.alb(wire_mgl_prim1_alb),
-	.dataa(dataa),
-	.datab(datab));
-	defparam
-		mgl_prim1.lpm_representation = "UNSIGNED",
-		mgl_prim1.lpm_type = "LPM_COMPARE",
-		mgl_prim1.lpm_width = 23;
-	assign
-		alb = wire_mgl_prim1_alb;
-endmodule //mgtbb
-//VALID FILE
-- 
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