From 4762ef9b7238f67d065775b752ebf51289c1f437 Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Sun, 15 Jun 2014 15:28:10 +0200 Subject: Clean project --- FPGA/pwm/greybox_tmp/cbx_args.txt | 7 -- FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v | 52 ------------- FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v | 51 ------------ FPGA/pwm/lpm_counter0.bsf | 64 --------------- FPGA/pwm/lpm_counter0.cmp | 23 ------ FPGA/pwm/lpm_counter0.qip | 5 -- FPGA/pwm/lpm_counter0.vhd | 130 ------------------------------- FPGA/pwm/pwm.qsf | 1 - FPGA/pwm/pwm.qws | Bin 1406 -> 2168 bytes FPGA/pwm/pwm.tcl | 88 +++++++++++++++++++-- 10 files changed, 82 insertions(+), 339 deletions(-) delete mode 100644 FPGA/pwm/greybox_tmp/cbx_args.txt delete mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v delete mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v delete mode 100644 FPGA/pwm/lpm_counter0.bsf delete mode 100644 FPGA/pwm/lpm_counter0.cmp delete mode 100644 FPGA/pwm/lpm_counter0.qip delete mode 100644 FPGA/pwm/lpm_counter0.vhd (limited to 'FPGA/pwm') diff --git a/FPGA/pwm/greybox_tmp/cbx_args.txt b/FPGA/pwm/greybox_tmp/cbx_args.txt deleted file mode 100644 index 662f251..0000000 --- a/FPGA/pwm/greybox_tmp/cbx_args.txt +++ /dev/null @@ -1,7 +0,0 @@ -LPM_REPRESENTATION=UNSIGNED -LPM_TYPE=LPM_COMPARE -LPM_WIDTH=23 -DEVICE_FAMILY="Cyclone II" -dataa -datab -alb diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v deleted file mode 100644 index 90c1893..0000000 --- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v +++ /dev/null @@ -1,52 +0,0 @@ -//lpm_mux CBX_SINGLE_OUTPUT_FILE="ON" LPM_SIZE=4 LPM_TYPE="LPM_MUX" LPM_WIDTH=1 LPM_WIDTHS=2 data result sel -//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ VERSION_END -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - - -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - - -//synthesis_resources = lpm_mux 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module mgbt9 - ( - data, - result, - sel) /* synthesis synthesis_clearbox=1 */; - input [3:0] data; - output [0:0] result; - input [1:0] sel; - - wire [0:0] wire_mgl_prim1_result; - - lpm_mux mgl_prim1 - ( - .data(data), - .result(wire_mgl_prim1_result), - .sel(sel)); - defparam - mgl_prim1.lpm_size = 4, - mgl_prim1.lpm_type = "LPM_MUX", - mgl_prim1.lpm_width = 1, - mgl_prim1.lpm_widths = 2; - assign - result = wire_mgl_prim1_result; -endmodule //mgbt9 -//VALID FILE diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v deleted file mode 100644 index 8fab5c3..0000000 --- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v +++ /dev/null @@ -1,51 +0,0 @@ -//lpm_compare CBX_SINGLE_OUTPUT_FILE="ON" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_COMPARE" LPM_WIDTH=23 alb dataa datab -//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ VERSION_END -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - - -// Copyright (C) 1991-2013 Altera Corporation -// Your use of Altera Corporation's design tools, logic functions -// and other software and tools, and its AMPP partner logic -// functions, and any output files from any of the foregoing -// (including device programming or simulation files), and any -// associated documentation or information are expressly subject -// to the terms and conditions of the Altera Program License -// Subscription Agreement, Altera MegaCore Function License -// Agreement, or other applicable license agreement, including, -// without limitation, that your use is for the sole purpose of -// programming logic devices manufactured by Altera and sold by -// Altera or its authorized distributors. Please refer to the -// applicable agreement for further details. - - - -//synthesis_resources = lpm_compare 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module mgtbb - ( - alb, - dataa, - datab) /* synthesis synthesis_clearbox=1 */; - output alb; - input [22:0] dataa; - input [22:0] datab; - - wire wire_mgl_prim1_alb; - - lpm_compare mgl_prim1 - ( - .alb(wire_mgl_prim1_alb), - .dataa(dataa), - .datab(datab)); - defparam - mgl_prim1.lpm_representation = "UNSIGNED", - mgl_prim1.lpm_type = "LPM_COMPARE", - mgl_prim1.lpm_width = 23; - assign - alb = wire_mgl_prim1_alb; -endmodule //mgtbb -//VALID FILE diff --git a/FPGA/pwm/lpm_counter0.bsf b/FPGA/pwm/lpm_counter0.bsf deleted file mode 100644 index 5cc02c4..0000000 --- a/FPGA/pwm/lpm_counter0.bsf +++ /dev/null @@ -1,64 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2013 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 144 96) - (text "lpm_counter0" (rect 33 0 129 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 81 26 92)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)) - ) - (port - (pt 80 96) - (input) - (text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical)) - (text "aclr" (rect 74 57 86 75)(font "Arial" (font_size 8))(vertical)) - (line (pt 80 96)(pt 80 80)) - ) - (port - (pt 144 40) - (output) - (text "q[18..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "q[18..0]" (rect 89 34 126 46)(font "Arial" (font_size 8))) - (line (pt 144 40)(pt 128 40)(line_width 3)) - ) - (drawing - (text "up counter" (rect 84 23 214 56)(font "Arial" )) - (line (pt 16 16)(pt 16 80)) - (line (pt 16 16)(pt 128 16)) - (line (pt 16 80)(pt 128 80)) - (line (pt 128 16)(pt 128 80)) - (line (pt 0 0)(pt 146 0)) - (line (pt 146 0)(pt 146 98)) - (line (pt 0 98)(pt 146 98)) - (line (pt 0 0)(pt 0 98)) - (line (pt 16 26)(pt 22 32)) - (line (pt 22 32)(pt 16 38)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - (line (pt 0 0)(pt 0 0)) - ) -) diff --git a/FPGA/pwm/lpm_counter0.cmp b/FPGA/pwm/lpm_counter0.cmp deleted file mode 100644 index f505116..0000000 --- a/FPGA/pwm/lpm_counter0.cmp +++ /dev/null @@ -1,23 +0,0 @@ ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component lpm_counter0 - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0) - ); -end component; diff --git a/FPGA/pwm/lpm_counter0.qip b/FPGA/pwm/lpm_counter0.qip deleted file mode 100644 index f7b47d7..0000000 --- a/FPGA/pwm/lpm_counter0.qip +++ /dev/null @@ -1,5 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] diff --git a/FPGA/pwm/lpm_counter0.vhd b/FPGA/pwm/lpm_counter0.vhd deleted file mode 100644 index 9a8bd70..0000000 --- a/FPGA/pwm/lpm_counter0.vhd +++ /dev/null @@ -1,130 +0,0 @@ --- megafunction wizard: %LPM_COUNTER% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: LPM_COUNTER - --- ============================================================ --- File Name: lpm_counter0.vhd --- Megafunction Name(s): --- LPM_COUNTER --- --- Simulation Library Files(s): --- lpm --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2013 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY lpm; -USE lpm.all; - -ENTITY lpm_counter0 IS - PORT - ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0) - ); -END lpm_counter0; - - -ARCHITECTURE SYN OF lpm_counter0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (18 DOWNTO 0); - - - - COMPONENT lpm_counter - GENERIC ( - lpm_direction : STRING; - lpm_port_updown : STRING; - lpm_type : STRING; - lpm_width : NATURAL - ); - PORT ( - aclr : IN STD_LOGIC ; - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(18 DOWNTO 0); - - LPM_COUNTER_component : LPM_COUNTER - GENERIC MAP ( - lpm_direction => "UP", - lpm_port_updown => "PORT_UNUSED", - lpm_type => "LPM_COUNTER", - lpm_width => 19 - ) - PORT MAP ( - aclr => aclr, - clock => clock, - q => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACLR NUMERIC "1" --- Retrieval info: PRIVATE: ALOAD NUMERIC "0" --- Retrieval info: PRIVATE: ASET NUMERIC "0" --- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" --- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" --- Retrieval info: PRIVATE: CarryIn NUMERIC "0" --- Retrieval info: PRIVATE: CarryOut NUMERIC "0" --- Retrieval info: PRIVATE: Direction NUMERIC "0" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" --- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" --- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" --- Retrieval info: PRIVATE: SCLR NUMERIC "0" --- Retrieval info: PRIVATE: SLOAD NUMERIC "0" --- Retrieval info: PRIVATE: SSET NUMERIC "0" --- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: nBit NUMERIC "19" --- Retrieval info: PRIVATE: new_diagram STRING "1" --- Retrieval info: LIBRARY: lpm lpm.lpm_components.all --- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" --- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "19" --- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" --- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" --- Retrieval info: USED_PORT: q 0 0 19 0 OUTPUT NODEFVAL "q[18..0]" --- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 --- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 --- Retrieval info: CONNECT: q 0 0 19 0 @q 0 0 19 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE --- Retrieval info: LIB_FILE: lpm diff --git a/FPGA/pwm/pwm.qsf b/FPGA/pwm/pwm.qsf index 5cd6136..39f5397 100644 --- a/FPGA/pwm/pwm.qsf +++ b/FPGA/pwm/pwm.qsf @@ -49,7 +49,6 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name BDF_FILE pwm.bdf -set_global_assignment -name QIP_FILE lpm_counter0.qip set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_constant0.qip set_global_assignment -name QIP_FILE lpm_constant1.qip diff --git a/FPGA/pwm/pwm.qws b/FPGA/pwm/pwm.qws index 2d3a416..6031e35 100644 Binary files a/FPGA/pwm/pwm.qws and b/FPGA/pwm/pwm.qws differ diff --git a/FPGA/pwm/pwm.tcl b/FPGA/pwm/pwm.tcl index 267245a..bda2614 100644 --- a/FPGA/pwm/pwm.tcl +++ b/FPGA/pwm/pwm.tcl @@ -1,6 +1,82 @@ -set_location_assignment PIN_P25 -to speed[0] -set_location_assignment PIN_AE14 -to speed[1] -set_location_assignment PIN_N2 -to clk -set_location_assignment PIN_G26 -to resetn -set_location_assignment PIN_K26 -to fan -set_location_assignment PIN_Y18 -to led_fan +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +# Quartus II: Generate Tcl File for Project +# File: pwm.tcl +# Generated on: Sun Jun 15 15:04:34 2014 + +# Load Quartus II Tcl Project package +package require ::quartus::project + +set need_to_close_project 0 +set make_assignments 1 + +# Check that the right project is open +if {[is_project_open]} { + if {[string compare $quartus(project) "pwm"]} { + puts "Project pwm is not open" + set make_assignments 0 + } +} else { + # Only open if not already open + if {[project_exists pwm]} { + project_open -revision pwm pwm + } else { + project_new -revision pwm pwm + } + set need_to_close_project 1 +} + +# Make assignments +if {$make_assignments} { + set_global_assignment -name FAMILY "Cyclone II" + set_global_assignment -name DEVICE EP2C35F672C6 + set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:34:57 MAY 05, 2014" + set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" + set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 + set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + set_global_assignment -name USE_CONFIGURATION_DEVICE ON + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" + set_global_assignment -name BDF_FILE pwm.bdf + set_global_assignment -name QIP_FILE lpm_mux0.qip + set_global_assignment -name QIP_FILE lpm_constant0.qip + set_global_assignment -name QIP_FILE lpm_constant1.qip + set_global_assignment -name QIP_FILE lpm_constant2.qip + set_global_assignment -name QIP_FILE lpm_constant3.qip + set_global_assignment -name QIP_FILE lpm_counter1.qip + set_global_assignment -name QIP_FILE lpm_compare0.qip + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_location_assignment PIN_N2 -to clk + set_location_assignment PIN_G26 -to resetn + set_location_assignment PIN_K26 -to fan + set_location_assignment PIN_Y18 -to led_fan + set_location_assignment PIN_P25 -to speed[0] + set_location_assignment PIN_AE14 -to speed[1] + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + + # Commit assignments + export_assignments + + # Close project + if {$need_to_close_project} { + project_close + } +} -- cgit v1.2.3