From 4762ef9b7238f67d065775b752ebf51289c1f437 Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Sun, 15 Jun 2014 15:28:10 +0200
Subject: Clean project

---
 FPGA/sound_gene/sound_gene.tcl | 98 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 FPGA/sound_gene/sound_gene.tcl

(limited to 'FPGA/sound_gene/sound_gene.tcl')

diff --git a/FPGA/sound_gene/sound_gene.tcl b/FPGA/sound_gene/sound_gene.tcl
new file mode 100644
index 0000000..0f363d8
--- /dev/null
+++ b/FPGA/sound_gene/sound_gene.tcl
@@ -0,0 +1,98 @@
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: sound_gene.tcl
+# Generated on: Sun Jun 15 15:22:44 2014
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+	if {[string compare $quartus(project) "sound_gene"]} {
+		puts "Project sound_gene is not open"
+		set make_assignments 0
+	}
+} else {
+	# Only open if not already open
+	if {[project_exists sound_gene]} {
+		project_open -revision sound_gene sound_gene
+	} else {
+		project_new -revision sound_gene sound_gene
+	}
+	set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+	set_global_assignment -name FAMILY "Cyclone II"
+	set_global_assignment -name DEVICE EP2C35F672C6
+	set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+	set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:03:18  MAI 26, 2014"
+	set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+	set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+	set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+	set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+	set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+	set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+	set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+	set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+	set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+	set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+	set_global_assignment -name BDF_FILE ../codec_clock/codec_clock.bdf
+	set_global_assignment -name BSF_FILE ../codec_clock/codec_clock.bsf
+	set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd
+	set_global_assignment -name VHDL_FILE ../vhdl/dds_sinus.vhd
+	set_global_assignment -name VHDL_FILE ../vhdl/rom_sinus.vhd
+	set_global_assignment -name VHDL_FILE ../vhdl/codec_dac.vhd
+	set_global_assignment -name VHDL_FILE ../vhdl/codec_config.vhd
+	set_global_assignment -name VHDL_FILE ../vhdl/i2c_master.vhd
+	set_global_assignment -name BDF_FILE sound_gene.bdf
+	set_location_assignment PIN_N25 -to alarm_user
+	set_location_assignment PIN_P25 -to speed_user[0]
+	set_location_assignment PIN_AE14 -to speed_user[1]
+	set_location_assignment PIN_N26 -to fan_auto_user
+	set_location_assignment PIN_AE23 -to alarm
+	set_location_assignment PIN_AF23 -to fan_auto
+	set_location_assignment PIN_AB21 -to speed[0]
+	set_location_assignment PIN_AC22 -to speed[1]
+	set_location_assignment PIN_N2 -to clk
+	set_location_assignment PIN_G26 -to resetn
+	set_location_assignment PIN_M23 -to hot
+	set_location_assignment PIN_K26 -to fan
+	set_location_assignment PIN_B4 -to aud_bclk
+	set_location_assignment PIN_A4 -to aud_dacdat
+	set_location_assignment PIN_C6 -to aud_daclrck
+	set_location_assignment PIN_A5 -to aud_xck
+	set_location_assignment PIN_A6 -to i2c_sclk
+	set_location_assignment PIN_B6 -to i2c_sdat
+	set_location_assignment PIN_M20 -to sound_high_level
+	set_location_assignment PIN_Y18 -to led_fan
+	set_location_assignment PIN_AE22 -to end_config
+	set_location_assignment PIN_M25 -to xti_mclk
+	set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+	# Commit assignments
+	export_assignments
+
+	# Close project
+	if {$need_to_close_project} {
+		project_close
+	}
+}
-- 
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