From 12bbdb42cdcf5e6e39832d75fbbd31e3781d550a Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 11 Apr 2014 19:29:53 +0200
Subject: Import fichiers projet Quartus

---
 FPGA/vhdl/codec_config.vhd | 92 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 FPGA/vhdl/codec_config.vhd

(limited to 'FPGA/vhdl/codec_config.vhd')

diff --git a/FPGA/vhdl/codec_config.vhd b/FPGA/vhdl/codec_config.vhd
new file mode 100644
index 0000000..2ae71f8
--- /dev/null
+++ b/FPGA/vhdl/codec_config.vhd
@@ -0,0 +1,92 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity codec_config is
+  generic (
+    system_frequency   : real := 50.0E6;   -- 50 MHz
+	  i2c_rate           : real := 20.0E3    -- 20 kHz	
+  );
+  port (
+    clk        : in    std_logic;
+	 resetn     : in    std_logic;
+	 end_config : out   std_logic;
+	 i2c_scl    : out   std_logic;
+	 i2c_sda    : inout std_logic
+  );
+end entity;
+
+architecture rtl of codec_config is
+  type t_config is array(natural range 0 to 10) of std_logic_vector(23 downto 0);
+  constant config_data : t_config :=
+              (X"34001A",
+						   X"34021A",
+						   X"34047B",
+						   X"34067B",
+						   X"3408F8",
+						   X"340A06",
+						   X"340C00",
+						   X"340E01",
+						   X"341002",
+						   X"341201",
+						   X"000000"
+						  );
+  type state is (init, config, finished);
+  signal i2c_data      : std_logic_vector(23 downto 0);
+  signal i2c_go        : std_logic;
+  signal i2c_ack       : std_logic;
+  signal i2c_ready     : std_logic;
+  signal ctr_data      : natural range 0 to 10;
+  signal current_state : state;  
+  
+begin
+
+  i2c_data      <= config_data(ctr_data);
+  
+  process(resetn, clk) is
+  begin
+    if resetn = '0' then 
+	  ctr_data      <= 0;
+	  current_state <= init;
+	  i2c_go        <= '0';
+	  end_config    <= '0';
+	elsif rising_edge(clk) then
+    case current_state is
+		  when init => i2c_go        <= '1';
+					         if i2c_ready = '0' then		              
+					            current_state <= config;
+					            ctr_data      <= ctr_data+1;
+					         end if;
+					      
+		  when config => i2c_go        <= '0';
+		                 if i2c_ready = '1' then		                   
+		                   if ctr_data<10 then
+		                     current_state <= init;		                     
+					             else 
+					               current_state <= finished;
+					             end if;  
+					           end if;					      
+		  when finished => end_config <= '1';
+		                   i2c_go     <= '0';
+		  end case;
+
+	end if;
+  end process;
+  
+  
+  i2c_ctrl : entity work.i2C_master
+    generic map (
+       system_frequency  => system_frequency,
+	     i2c_rate          => i2c_rate	
+    )
+    port map (
+      clk     => clk,
+	    resetn  => resetn,
+	    go      => i2c_go,
+	    ready   => i2c_ready,
+	    data_in => i2c_data,
+	    i2c_scl => i2c_scl,
+	    i2c_sda => i2c_sda,
+	    ack     => i2c_ack	
+  );
+end architecture;
\ No newline at end of file
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