From 12bbdb42cdcf5e6e39832d75fbbd31e3781d550a Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 11 Apr 2014 19:29:53 +0200
Subject: Import fichiers projet Quartus

---
 FPGA/vhdl/lcd.vhd | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 FPGA/vhdl/lcd.vhd

(limited to 'FPGA/vhdl/lcd.vhd')

diff --git a/FPGA/vhdl/lcd.vhd b/FPGA/vhdl/lcd.vhd
new file mode 100644
index 0000000..186aa52
--- /dev/null
+++ b/FPGA/vhdl/lcd.vhd
@@ -0,0 +1,89 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+entity lcd is 
+        generic (board_frequency : real := 50_000_000.0);   
+        port( 
+        clk           : in  std_logic;                      
+        resetn        : in  std_logic;   
+        
+        -- User Interface                 
+        ready         : out std_logic; 
+        mode          : in  std_logic_vector(1 downto 0);
+        char          : in  std_logic_vector(7 downto 0);
+        address       : in  std_logic_vector(6 downto 0);
+        write_char    : in  std_logic;
+        write_address : in  std_logic;
+        
+        D             : in  std_logic;
+        C             : in  std_logic;
+        B             : in  std_logic;
+       
+        -- lcd signals
+        lcd_data      : inout std_logic_vector(7 downto 0); 
+        lcd_on        : out std_logic;
+        lcd_blon      : out std_logic;
+        lcd_rs        : out std_logic;               
+        lcd_rw        : out std_logic;               
+        lcd_en        : out std_logic                 
+        );
+end entity;
+
+architecture rtl of lcd is 
+
+    signal en_user      : std_logic;  
+    signal lcd_data_int : std_logic_vector(lcd_data'range);
+    signal lcd_rs_int   : std_logic;  
+    signal lcd_en_int   : std_logic;
+    
+begin
+ 
+--------------------------------
+-- lcd
+--------------------------------
+lcd_on   <= '1';
+lcd_blon <= '1';
+
+  ctrl :   entity work.lcd_Controller
+    port map( 
+        Clk           => clk,
+        resetn        => resetn,
+        en_250kHz     => en_user,
+        char          => char,
+        D             => D,
+        C             => C,
+        B             => B,
+        write_char    => write_char,
+        mode          => mode,
+        address       => address,
+        write_address => write_address,
+        ready         => ready,
+        lcd_data      => lcd_data_int,
+        lcd_RS        => lcd_rs_int,
+        lcd_RW        => lcd_rw,
+        lcd_EN        => lcd_en_int
+        );
+ 
+ck : entity work.clock_divider
+  generic map (board_frequency => 50_000_000.0,
+               user_frequency  => 250_000.0 )
+  port map ( 
+       clk => clk,
+       resetn => resetn,
+       en_user => en_user
+  );     
+       process(resetn,clk) is          
+       begin
+            if resetn = '0' then               
+              lcd_data <= (others => '0');
+              lcd_rs   <= '0';
+              lcd_en   <= '0';                     
+            elsif rising_edge (clk) then                
+              lcd_data <= lcd_data_int;
+              lcd_rs   <= lcd_rs_int;
+              lcd_en   <= lcd_en_int;
+            end if;            
+       end process;  
+end architecture;
+    
\ No newline at end of file
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