From 12bbdb42cdcf5e6e39832d75fbbd31e3781d550a Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Fri, 11 Apr 2014 19:29:53 +0200
Subject: Import fichiers projet Quartus

---
 FPGA/vhdl/seven_segment_decoder.vhd | 72 +++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 FPGA/vhdl/seven_segment_decoder.vhd

(limited to 'FPGA/vhdl/seven_segment_decoder.vhd')

diff --git a/FPGA/vhdl/seven_segment_decoder.vhd b/FPGA/vhdl/seven_segment_decoder.vhd
new file mode 100644
index 0000000..8852319
--- /dev/null
+++ b/FPGA/vhdl/seven_segment_decoder.vhd
@@ -0,0 +1,72 @@
+-------------------------------------------
+-- decodeur 7 segments
+-------------------------------------------
+-- ESIEE
+-- Creation     : A. Exertier, novembre 2004
+-- Modification : A. Exertier, decembre 2011
+-------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+---------------------------------------------------
+--            Parametre generique
+---------------------------------------------------
+-- active_low : true  => segment allume par 0
+--              false => segment allume par 1
+---------------------------------------------------
+--           Entrees/sorties
+---------------------------------------------------
+-- hexa 	    : entree code hexadacimal (4 bits)
+-- abcdefg   : sortie 7 segments
+--		a : segment horizontal superieur
+--      a est le MSB de abcdefg
+--		b : segment vertical superieur droit
+--		c : segment vertical inferieur droit
+--		d : segment horizontal inferieur
+--		e : segment vertical indefieur gauche
+--		f : segment vertical superieur gauche
+--		g : segment horizontal milieu
+---------------------------------------------------
+
+entity seven_segment_decoder  is
+  generic (active_low : boolean := true);
+  port (hexa    : in  std_logic_vector(3 downto 0);
+        hex     : out std_logic_vector(6 downto 0));
+end ;
+
+
+architecture RTL of  seven_segment_decoder is
+  signal segments : std_logic_vector(hex'range);
+  signal abcdefg  : std_logic_vector(hex'range);
+begin
+ abcdefg <= segments when active_low else  not segments;
+ process(abcdefg) is
+ begin
+   for i in hex'range loop
+	   hex(i) <= abcdefg(hex'length-1-i);
+	end loop;
+ end process;
+ 
+ process(hexa)
+ begin
+  case hexa is
+    when "0000" => segments <= "0000001";  -- 0
+    when "0001" => segments <= "1001111";  -- 1
+    when "0010" => segments <= "0010010";  -- 2
+    when "0011" => segments <= "0000110";  -- 3
+    when "0100" => segments <= "1001100";  -- 4
+    when "0101" => segments <= "0100100";  -- 5
+    when "0110" => segments <= "0100000";  -- 6
+    when "0111" => segments <= "0001111";  -- 7
+    when "1000" => segments <= "0000000";  -- 8
+    when "1001" => segments <= "0000100";  -- 9
+    when "1010" => segments <= "0001000";  -- A
+    when "1011" => segments <= "1100000";  -- B
+    when "1100" => segments <= "0110001";  -- C
+    when "1101" => segments <= "1000010";  -- D
+    when "1110" => segments <= "0110000";  -- E
+    when "1111" => segments <= "0111000";  -- F
+    when others => segments <= "1111111";
+  end case;
+ end process;
+end ;
-- 
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