From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Fri, 13 Jun 2014 16:06:19 +0200 Subject: Update project --- FPGA/vhdl/LCD_message.bdf | 415 +++++++++++++++++++++++++++++ FPGA/vhdl/codec_config.vhd | 21 +- FPGA/vhdl/dds_sinus.vhd | 4 +- FPGA/vhdl/greybox_tmp/cbx_args.txt | 12 + FPGA/vhdl/i2c_master.vhd | 526 +++++++++++++++++++------------------ FPGA/vhdl/lpm_shiftreg0.qip | 0 FPGA/vhdl/message.vhd | 66 ++--- FPGA/vhdl/message.vhd.bak | 67 +++++ 8 files changed, 813 insertions(+), 298 deletions(-) create mode 100644 FPGA/vhdl/LCD_message.bdf create mode 100644 FPGA/vhdl/greybox_tmp/cbx_args.txt create mode 100644 FPGA/vhdl/lpm_shiftreg0.qip create mode 100644 FPGA/vhdl/message.vhd.bak (limited to 'FPGA/vhdl') diff --git a/FPGA/vhdl/LCD_message.bdf b/FPGA/vhdl/LCD_message.bdf new file mode 100644 index 0000000..71d3ff7 --- /dev/null +++ b/FPGA/vhdl/LCD_message.bdf @@ -0,0 +1,415 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 80 56 248 72) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 21 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 24 72 80 88)) +) +(pin + (input) + (rect 80 72 248 88) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "resetn" (rect 5 0 37 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 16 88 80 104)) +) +(pin + (output) + (rect 80 104 256 120) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "lcd_rs" (rect 90 0 120 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 256 120 312 136)) +) +(pin + (output) + (rect 80 120 256 136) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "lcd_on" (rect 90 0 124 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 256 136 312 152)) +) +(pin + (output) + (rect 80 136 256 152) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "lcd_data[7..0]" (rect 90 0 156 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 256 152 312 168)) +) +(pin + (output) + (rect 80 152 256 168) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "lcd_blon" (rect 90 0 132 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 256 168 312 184)) +) +(pin + (output) + (rect 80 168 256 184) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "lcd_en" (rect 90 0 124 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 256 184 312 200)) +) +(symbol + (rect 544 56 760 296) + (text "LCD_controller" (rect 5 0 81 11)(font "Arial" )) + (text "inst" (rect 8 224 26 235)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 15 11)(font "Arial" )) + (text "clk" (rect 21 27 36 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 31 11)(font "Arial" )) + (text "resetn" (rect 21 43 52 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "en_250kHz" (rect 0 0 57 11)(font "Arial" )) + (text "en_250kHz" (rect 21 59 78 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "mode[1..0]" (rect 0 0 53 11)(font "Arial" )) + (text "mode[1..0]" (rect 21 75 74 86)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 0 96) + (input) + (text "char[7..0]" (rect 0 0 46 11)(font "Arial" )) + (text "char[7..0]" (rect 21 91 67 102)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address[6..0]" (rect 0 0 63 11)(font "Arial" )) + (text "address[6..0]" (rect 21 107 84 118)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "write_char" (rect 0 0 53 11)(font "Arial" )) + (text "write_char" (rect 21 123 74 134)(font "Arial" )) + (line (pt 0 128)(pt 16 128)) + ) + (port + (pt 0 144) + (input) + (text "write_address" (rect 0 0 69 11)(font "Arial" )) + (text "write_address" (rect 21 139 90 150)(font "Arial" )) + (line (pt 0 144)(pt 16 144)) + ) + (port + (pt 0 160) + (input) + (text "D" (rect 0 0 9 11)(font "Arial" )) + (text "D" (rect 21 155 30 166)(font "Arial" )) + (line (pt 0 160)(pt 16 160)) + ) + (port + (pt 0 176) + (input) + (text "C" (rect 0 0 9 11)(font "Arial" )) + (text "C" (rect 21 171 30 182)(font "Arial" )) + (line (pt 0 176)(pt 16 176)) + ) + (port + (pt 0 192) + (input) + (text "B" (rect 0 0 9 11)(font "Arial" )) + (text "B" (rect 21 187 30 198)(font "Arial" )) + (line (pt 0 192)(pt 16 192)) + ) + (port + (pt 216 32) + (output) + (text "ready" (rect 0 0 29 11)(font "Arial" )) + (text "ready" (rect 171 27 200 38)(font "Arial" )) + (line (pt 216 32)(pt 200 32)) + ) + (port + (pt 216 64) + (output) + (text "LCD_RS" (rect 0 0 44 11)(font "Arial" )) + (text "LCD_RS" (rect 158 59 202 70)(font "Arial" )) + (line (pt 216 64)(pt 200 64)) + ) + (port + (pt 216 80) + (output) + (text "LCD_RW" (rect 0 0 48 11)(font "Arial" )) + (text "LCD_RW" (rect 155 75 203 86)(font "Arial" )) + (line (pt 216 80)(pt 200 80)) + ) + (port + (pt 216 96) + (output) + (text "LCD_EN" (rect 0 0 43 11)(font "Arial" )) + (text "LCD_EN" (rect 159 91 202 102)(font "Arial" )) + (line (pt 216 96)(pt 200 96)) + ) + (port + (pt 216 48) + (bidir) + (text "LCD_data[7..0]" (rect 0 0 74 11)(font "Arial" )) + (text "LCD_data[7..0]" (rect 133 43 207 54)(font "Arial" )) + (line (pt 216 48)(pt 200 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 224)) + ) +) +(symbol + (rect 816 192 1024 400) + (text "lcd" (rect 5 0 20 11)(font "Arial" )) + (text "inst2" (rect 8 192 32 203)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 15 11)(font "Arial" )) + (text "clk" (rect 21 27 36 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 31 11)(font "Arial" )) + (text "resetn" (rect 21 43 52 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "mode[1..0]" (rect 0 0 53 11)(font "Arial" )) + (text "mode[1..0]" (rect 21 59 74 70)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "char[7..0]" (rect 0 0 46 11)(font "Arial" )) + (text "char[7..0]" (rect 21 75 67 86)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 0 96) + (input) + (text "address[6..0]" (rect 0 0 63 11)(font "Arial" )) + (text "address[6..0]" (rect 21 91 84 102)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "write_char" (rect 0 0 53 11)(font "Arial" )) + (text "write_char" (rect 21 107 74 118)(font "Arial" )) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 0 128) + (input) + (text "write_address" (rect 0 0 69 11)(font "Arial" )) + (text "write_address" (rect 21 123 90 134)(font "Arial" )) + (line (pt 0 128)(pt 16 128)) + ) + (port + (pt 0 144) + (input) + (text "D" (rect 0 0 9 11)(font "Arial" )) + (text "D" (rect 21 139 30 150)(font "Arial" )) + (line (pt 0 144)(pt 16 144)) + ) + (port + (pt 0 160) + (input) + (text "C" (rect 0 0 9 11)(font "Arial" )) + (text "C" (rect 21 155 30 166)(font "Arial" )) + (line (pt 0 160)(pt 16 160)) + ) + (port + (pt 0 176) + (input) + (text "B" (rect 0 0 9 11)(font "Arial" )) + (text "B" (rect 21 171 30 182)(font "Arial" )) + (line (pt 0 176)(pt 16 176)) + ) + (port + (pt 208 32) + (output) + (text "ready" (rect 0 0 29 11)(font "Arial" )) + (text "ready" (rect 163 27 192 38)(font "Arial" )) + (line (pt 208 32)(pt 192 32)) + ) + (port + (pt 208 64) + (output) + (text "lcd_on" (rect 0 0 34 11)(font "Arial" )) + (text "lcd_on" (rect 159 59 193 70)(font "Arial" )) + (line (pt 208 64)(pt 192 64)) + ) + (port + (pt 208 80) + (output) + (text "lcd_blon" (rect 0 0 42 11)(font "Arial" )) + (text "lcd_blon" (rect 152 75 194 86)(font "Arial" )) + (line (pt 208 80)(pt 192 80)) + ) + (port + (pt 208 96) + (output) + (text "lcd_rs" (rect 0 0 30 11)(font "Arial" )) + (text "lcd_rs" (rect 162 91 192 102)(font "Arial" )) + (line (pt 208 96)(pt 192 96)) + ) + (port + (pt 208 112) + (output) + (text "lcd_rw" (rect 0 0 33 11)(font "Arial" )) + (text "lcd_rw" (rect 160 107 193 118)(font "Arial" )) + (line (pt 208 112)(pt 192 112)) + ) + (port + (pt 208 128) + (output) + (text "lcd_en" (rect 0 0 34 11)(font "Arial" )) + (text "lcd_en" (rect 159 123 193 134)(font "Arial" )) + (line (pt 208 128)(pt 192 128)) + ) + (port + (pt 208 48) + (bidir) + (text "lcd_data[7..0]" (rect 0 0 66 11)(font "Arial" )) + (text "lcd_data[7..0]" (rect 134 43 200 54)(font "Arial" )) + (line (pt 208 48)(pt 192 48)(line_width 3)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 192 192)) + ) + (annotation_block (parameter)(rect 1024 160 1216 192)) +) +(symbol + (rect 480 352 648 432) + (text "message" (rect 5 0 51 11)(font "Arial" )) + (text "inst3" (rect 8 64 32 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "adr[4..0]" (rect 0 0 41 11)(font "Arial" )) + (text "adr[4..0]" (rect 21 27 62 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 168 32) + (output) + (text "do[7..0]" (rect 0 0 37 11)(font "Arial" )) + (text "do[7..0]" (rect 116 27 153 38)(font "Arial" )) + (line (pt 168 32)(pt 152 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 152 64)) + ) +) diff --git a/FPGA/vhdl/codec_config.vhd b/FPGA/vhdl/codec_config.vhd index 2ae71f8..69c661c 100644 --- a/FPGA/vhdl/codec_config.vhd +++ b/FPGA/vhdl/codec_config.vhd @@ -19,16 +19,17 @@ end entity; architecture rtl of codec_config is type t_config is array(natural range 0 to 10) of std_logic_vector(23 downto 0); constant config_data : t_config := - (X"34001A", - X"34021A", - X"34047B", - X"34067B", - X"3408F8", - X"340A06", - X"340C00", - X"340E01", - X"341002", - X"341201", + ( + X"34001A", -- X"34001A", + X"34021A", -- X"34021A", + X"34047F", -- X"34047B", -- headphone left => doit etre on pour mono + X"340600", -- X"34067B", -- headphone right + X"3408F8", -- X"3408F8", + X"340A07", -- X"340A06", + X"340C00", -- X"340C00", -- power on + X"340E01", -- X"340E01", + X"341002", -- X"341002", -- sample control + X"341201", -- X"341201", -- set active X"000000" ); type state is (init, config, finished); diff --git a/FPGA/vhdl/dds_sinus.vhd b/FPGA/vhdl/dds_sinus.vhd index d47f290..1de67d8 100644 --- a/FPGA/vhdl/dds_sinus.vhd +++ b/FPGA/vhdl/dds_sinus.vhd @@ -37,14 +37,14 @@ entity dds_sinus is port ( resetn : in std_logic; clk : in std_logic; - en : in std_logic; - incr_step : in std_logic_vector(M-1 downto 0); + en : in std_logic; dds_out : out std_logic_vector(N_data-1 downto 0) ); end dds_sinus; architecture RTL of dds_sinus is constant amplitude : positive :=2**(N_data-1)-1; + constant incr_step : std_logic_vector(M-1 downto 0):= (0=>'1', others => '0'); constant N_adr_ROM : positive := M-2; constant middle : unsigned (N_data-1 downto 0) := to_unsigned(2**(dds_out'length-1),dds_out'length); --(N_data-1=>'1', others => '0'); diff --git a/FPGA/vhdl/greybox_tmp/cbx_args.txt b/FPGA/vhdl/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..652a593 --- /dev/null +++ b/FPGA/vhdl/greybox_tmp/cbx_args.txt @@ -0,0 +1,12 @@ +LPM_AVALUE=000000000001 +LPM_DIRECTION=LEFT +LPM_TYPE=LPM_SHIFTREG +LPM_WIDTH=12 +DEVICE_FAMILY="Cyclone II" +aclr +aset +clock +enable +shiftin +q +shiftout diff --git a/FPGA/vhdl/i2c_master.vhd b/FPGA/vhdl/i2c_master.vhd index 99b179b..bc0381e 100644 --- a/FPGA/vhdl/i2c_master.vhd +++ b/FPGA/vhdl/i2c_master.vhd @@ -1,255 +1,271 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity i2C_master is - generic ( - system_frequency : real := 50.0E6; -- 50 MHz - i2c_rate : real := 20.0E3 -- 20 kHz - ); - port ( - clk : in std_logic; - resetn : in std_logic; - go : in std_logic; - ready : out std_logic; - data_in : in std_logic_vector(23 downto 0); -- adress & command & data - ack : out std_logic; - -- i2c - i2c_scl : out std_logic; -- A6 - i2c_sda : inout std_logic -- B6 - ); -end entity; - -architecture rtl of i2c_master is - constant mod_ctr_tempo : positive := integer(system_frequency/(2.0*i2c_rate)); - constant mod_ctr_bit : positive := 35; - type state is (wait_for_go, wait_for_i2clk, tx); - signal current_state : state; - signal next_state : state; - signal sdo : std_logic; - signal ctr_tempo : natural range 0 to mod_ctr_tempo-1; - signal end_tempo : std_logic; - signal ctr_bit : natural range 0 to mod_ctr_bit-1; - signal ack1 : std_logic; - signal ack2 : std_logic; - signal ack3 : std_logic; - signal reg_data : std_logic_vector(data_in'range); - signal cmd_data : std_logic_vector(1 downto 0); - signal cmd_bit : std_logic_vector(1 downto 0); - signal cmd_ack1 : std_logic_vector(1 downto 0); - signal cmd_ack2 : std_logic_vector(1 downto 0); - signal cmd_ack3 : std_logic_vector(1 downto 0); - signal sclk : std_logic; - signal i2c_clk : std_logic; - signal ready_i : std_logic; - -begin - i2c_sda <= 'Z' when sdo = '1' - else '0'; - i2c_scl <= '1' when sclk='1' - else not i2c_clk when (ctr_bit>=4 and ctr_bit <= 30) - else '0'; - ack <= ack1 or ack2 or ack3; - end_tempo <= '0' when ctr_tempo< mod_ctr_tempo-1 else '1'; - - process(resetn, clk) is - begin - if resetn = '0' then - i2c_clk <= '0'; - ctr_tempo <= 0; - ctr_bit <= 0; - reg_data <= (others => '0'); - --sclk <= '1'; - ACK1 <= '0'; - ACK2 <= '0'; - ACK3 <= '0'; - ready <= '1'; - current_state <= wait_for_go; - elsif rising_edge(clk) then - current_state <= next_state; - ready <= ready_i; - - -- temporisation et i2_clk - if current_state = wait_for_go then - ctr_tempo <= 0; - i2c_clk <= '0'; - elsif end_tempo='0' then - ctr_tempo <= ctr_tempo +1; - else - ctr_tempo <= 0; - i2c_clk <= not i2c_clk; - end if; - -- reg_data - case cmd_data is - when "10" => reg_data <= data_in; - when "11" => reg_data <= reg_data(22 downto 0)&'0'; - when others => null; - end case; - -- ctr_bit - case cmd_bit is - when "10" => ctr_bit <= 0; - when "11" => if ctr_bit null; - end case; - -- ack1 - case cmd_ack1 is - when "10" => ack1 <= '0'; - when "11" => ack1 <= '1'; - when others => null; - end case; - -- ack2 - case cmd_ack2 is - when "10" => ack2 <= '0'; - when "11" => ack2 <= '1'; - when others => null; - end case; - -- ack1 - case cmd_ack3 is - when "10" => ack3 <= '0'; - when "11" => ack3 <= '1'; - when others => null; - end case; - end if; -end process; --------------------------------- --- FSM -------------------------------- -process(current_state, end_tempo, i2c_clk, go,reg_data(23), i2c_sda,ctr_bit) is -begin - next_state <= current_state; - ready_i <= '0'; - cmd_ack1 <= "00"; - cmd_ack2 <= "00"; - cmd_ack3 <= "00"; - cmd_bit <= "00"; - cmd_data <= "00"; - sdo <= '1'; - sclk <= '0'; - case current_state is - when wait_for_go => if go = '1' then next_state <=wait_for_i2clk; - end if; - ready_i <= '1'; - cmd_bit <= "10"; - cmd_data <= "10"; - sclk <= '1'; - when wait_for_i2clk => if i2c_clk='0' and end_tempo='1' then next_state <=tx; - end if; - cmd_ack1 <= "10"; - cmd_ack2 <= "10"; - cmd_ack3 <= "10"; - sclk <= '1'; - when tx => if ctr_bit< mod_ctr_bit-1 then - if i2c_clk='0' and end_tempo='1'then - cmd_bit <= "11"; - end if; - elsif end_tempo='1'then - next_state <= wait_for_go; - end if; - case ctr_bit is - when 0 => sdo <= '1'; sclk <= '1'; - -- start - when 1 => sdo <= '0'; sclk <= '0'; - when 2 => sdo <= '0'; sclk <= '0'; - -- slave address - when 3 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 4 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 5 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 6 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 7 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 8 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 9 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 10 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 11 => sdo <= '1'; -- ack - - -- command - when 12 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - if i2c_sda='1' then cmd_ack1 <= "11" ; - else cmd_ack1 <= "10" ; - end if; - when 13 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 14 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 15 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 16 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 17 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 18 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 19 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 20 => sdo <= '1'; -- ack - -- data - when 21 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - if i2c_sda='1' then cmd_ack2 <= "11" ; - else cmd_ack2 <= "10" ; - end if; - when 22 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 23 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 24 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 25 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 26 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 27 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 28 => sdo <= reg_data(23); - if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; - end if; - when 29 => sdo <= '1'; -- ack - --stop - when 30 => sdo <= '0'; - if i2c_sda='1' then cmd_ack3 <= "11" ; - else cmd_ack3 <= "10" ; - end if; - sclk <= '0'; - when 31 => sdo <= '0'; sclk <= '1'; - when others => sdo <= '1'; sclk <= '1'; - end case; - - - end case; - -end process; - -end architecture; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2C_master is + generic ( + system_frequency : real := 50.0E6; -- 50 MHz + i2c_rate : real := 20.0E3 -- 20 kHz + ); + port ( + clk : in std_logic; + resetn : in std_logic; + go : in std_logic; + ready : out std_logic; + data_in : in std_logic_vector(23 downto 0); -- adress & command & data + ack : out std_logic; + -- i2c + i2c_scl : out std_logic; -- A6 + i2c_sda : inout std_logic -- B6 + ); +end entity; + +architecture rtl of i2c_master is + constant mod_ctr_tempo : positive := integer(system_frequency/(i2c_rate)); + constant mod_ctr_bit : positive := 35; + type state is (wait_for_go, wait_for_i2clk, tx, wait_for_not_go); + signal current_state : state; + signal next_state : state; + signal sdo : std_logic; + signal ctr_tempo : natural range 0 to mod_ctr_tempo-1; + signal end_tempo : std_logic; + signal ctr_bit : natural range 0 to mod_ctr_bit-1; + signal ack1 : std_logic; + signal ack2 : std_logic; + signal ack3 : std_logic; + signal reg_data : std_logic_vector(data_in'range); + signal cmd_data : std_logic_vector(1 downto 0); + signal cmd_bit : std_logic_vector(1 downto 0); + signal cmd_ack1 : std_logic_vector(1 downto 0); + signal cmd_ack2 : std_logic_vector(1 downto 0); + signal cmd_ack3 : std_logic_vector(1 downto 0); + signal sclk : std_logic; + signal i2c_clk : std_logic; + signal ready_i : std_logic; + +begin + i2c_sda <= 'Z' when sdo = '1' + else '0'; + i2c_scl <= '1' when sclk='1' + else not i2c_clk when (ctr_bit>=3 and ctr_bit <= 30) + else '0'; + ack <= ack1 or ack2 or ack3; + end_tempo <= '0' when ctr_tempo< mod_ctr_tempo-1 else '1'; + + process(resetn, clk) is + begin + if resetn = '0' then + i2c_clk <= '0'; + ctr_tempo <= 0; + ctr_bit <= 0; + reg_data <= (others => '0'); + --sclk <= '1'; + ACK1 <= '0'; + ACK2 <= '0'; + ACK3 <= '0'; + ready <= '1'; + current_state <= wait_for_go; + elsif rising_edge(clk) then + current_state <= next_state; + ready <= ready_i; + + -- temporisation et i2_clk + if current_state = wait_for_go then + ctr_tempo <= 0; + i2c_clk <= '0'; + elsif end_tempo='0' then + ctr_tempo <= ctr_tempo +1; + else + ctr_tempo <= 0; + i2c_clk <= not i2c_clk; + end if; + -- reg_data + case cmd_data is + when "10" => reg_data <= data_in; + when "11" => reg_data <= reg_data(22 downto 0)&'0'; + when others => null; + end case; + -- ctr_bit + case cmd_bit is + when "10" => ctr_bit <= 0; + when "11" => if ctr_bit null; + end case; + -- ack1 + case cmd_ack1 is + when "10" => ack1 <= '0'; + when "11" => ack1 <= '1'; + when others => null; + end case; + -- ack2 + case cmd_ack2 is + when "10" => ack2 <= '0'; + when "11" => ack2 <= '1'; + when others => null; + end case; + -- ack1 + case cmd_ack3 is + when "10" => ack3 <= '0'; + when "11" => ack3 <= '1'; + when others => null; + end case; + end if; +end process; +-------------------------------- +-- FSM +------------------------------- +process(current_state, end_tempo, i2c_clk, go,reg_data(23), i2c_sda,ctr_bit) is +begin + next_state <= current_state; + ready_i <= '0'; + cmd_ack1 <= "00"; + cmd_ack2 <= "00"; + cmd_ack3 <= "00"; + cmd_bit <= "00"; + cmd_data <= "00"; + sdo <= '1'; + sclk <= '0'; + case current_state is + when wait_for_not_go => if go = '0' then next_state <=wait_for_go; + end if; + ready_i <= '1'; + cmd_bit <= "10"; + cmd_data <= "10"; + sclk <= '1'; + when wait_for_go => if go = '1' then next_state <=wait_for_i2clk; + end if; + ready_i <= '1'; + cmd_bit <= "10"; + cmd_data <= "10"; + sclk <= '1'; + when wait_for_i2clk => if end_tempo='1' then next_state <=tx; cmd_bit <= "11"; + end if; + cmd_ack1 <= "10"; + cmd_ack2 <= "10"; + cmd_ack3 <= "10"; + sclk <= '1'; + when tx => if ctr_bit< mod_ctr_bit-1 then + if i2c_clk='0' and end_tempo='1'then + cmd_bit <= "11"; + end if; + elsif end_tempo='1'then + next_state <= wait_for_go; + end if; + case ctr_bit is + when 0 => sdo <= '1'; sclk <= '1'; + -- start + when 1 => sdo <= '0'; sclk <= '1'; + when 2 => sdo <= '0'; sclk <= '0'; + -- slave address + when 3 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 4 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 5 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 6 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 7 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 8 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 9 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 10 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 11 => sdo <= '1'; -- ack + if i2c_clk='0' and end_tempo='1' then + if i2c_sda='0' then cmd_ack1 <= "10" ; + else cmd_ack1 <= "11" ; + end if; + end if; + -- cmd_ack1 <= "11" ; + -- command + when 12 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + + when 13 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 14 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 15 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 16 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 17 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 18 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 19 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 20 => sdo <= '1'; -- ack + if i2c_clk='0' and end_tempo='1' then + if i2c_sda='0' then cmd_ack2 <= "10" ; + else cmd_ack2 <= "11" ; + end if; + end if; + -- cmd_ack2 <= "11" ; + -- data + when 21 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 22 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 23 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 24 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 25 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 26 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 27 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 28 => sdo <= reg_data(23); + if i2c_clk='0' and end_tempo='1'then cmd_data <= "11"; + end if; + when 29 => sdo <= '1'; -- ack + if i2c_clk='0' and end_tempo='1' then + if i2c_sda='0' then cmd_ack3 <= "10" ; + else cmd_ack3 <= "11" ; + end if; + end if; + -- cmd_ack3 <= "11" ; + --stop + when 30 => sdo <= '0'; + + sclk <= '0'; + when 31 => sdo <= '0'; sclk <= '1'; + when others => sdo <= '1'; sclk <= '1'; ready_i <= '1'; + end case; + + + end case; + +end process; + +end architecture; diff --git a/FPGA/vhdl/lpm_shiftreg0.qip b/FPGA/vhdl/lpm_shiftreg0.qip new file mode 100644 index 0000000..e69de29 diff --git a/FPGA/vhdl/message.vhd b/FPGA/vhdl/message.vhd index 09988e4..b8bccf1 100644 --- a/FPGA/vhdl/message.vhd +++ b/FPGA/vhdl/message.vhd @@ -27,39 +27,43 @@ architecture RTL of message is -- exemple T => 54 (en hexadecimal) -- 0=> X"54", indique que le 1er caractere (n°0) est un T -- Modifier les valeurs ASCII ci-dessous - 0 => X"54", -- T - 1 => X"68", -- h - 2 => X"65", -- e - 3 => X"20", -- - 4 => X"44", -- D - 5 => X"72", -- r - 6 => X"65", -- e - 7 => X"61", -- a - 8 => X"6D", -- m - 9 => X"20", -- - 10 => X"54", -- T - 11 => X"65", -- e - 12 => X"61", -- a - 13 => X"6D", -- m + + -- 53 63 69 65 6e 63 65 20 69 73 20 66 75 6e 21 + -- Science is fun! + + 0 => X"20", -- + 1 => X"53", -- S + 2 => X"63", -- c + 3 => X"69", -- i + 4 => X"65", -- e + 5 => X"6e", -- n + 6 => X"63", -- c + 7 => X"65", -- e + 8 => X"20", -- + 9 => X"20", -- + 10 => X"5E", -- ^ + 11 => X"20", -- + 12 => X"20", -- + 13 => X"5E", -- ^ 14 => X"20", -- - 15 => X"3A", -- : + 15 => X"20", -- -- 2eme ligne (de 15 caracteres) - 16 => X"43", -- C - 17 => X"6F", -- o - 18 => X"72", -- r - 19 => X"69", -- i - 20 => X"6E", -- n - 21 => X"6E", -- n - 22 => X"65", -- e - 23 => X"20", -- - 24 => X"65", -- e - 25 => X"74", -- t - 26 => X"20", -- - 27 => X"41", -- A - 28 => X"6E", -- n - 29 => X"6E", -- n - 30 => X"65", -- e - 31 => X"21" -- ! + 16 => X"20", -- + 17 => X"69", -- i + 18 => X"73", -- s + 19 => X"20", -- + 20 => X"66", -- f + 21 => X"75", -- u + 22 => X"6e", -- n + 23 => X"21", -- ! + 24 => X"20", -- + 25 => X"20", -- + 26 => X"60", -- _ + 27 => X"5F", -- _ + 28 => X"5F", -- _ + 29 => X"2F", -- / + 30 => X"20", -- + 31 => X"20" -- -- ne plus rien modifier en dessous de cette ligne ); begin diff --git a/FPGA/vhdl/message.vhd.bak b/FPGA/vhdl/message.vhd.bak new file mode 100644 index 0000000..09988e4 --- /dev/null +++ b/FPGA/vhdl/message.vhd.bak @@ -0,0 +1,67 @@ +------------------------------------------ +-- Message 32 characteres ASCII +-- ESIEE, JPO 2008 +-- Bienvenue +------------------------------------------ +-- Creation : A. Exertier, mars 2008 +-- Modification : A. Exertier, avril 2013 +------------------------------------------ + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity message is +port ( + adr : in std_logic_vector(4 downto 0); + do : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture RTL of message is + type contenu is array (0 to 31) of std_logic_vector(7 downto 0); + constant mes : contenu := ( + -- 1ere ligne (de 15 caracteres) + -- Mettre le code ASCII (en hexadecimal) de chaque caractère + -- exemple T => 54 (en hexadecimal) + -- 0=> X"54", indique que le 1er caractere (n°0) est un T + -- Modifier les valeurs ASCII ci-dessous + 0 => X"54", -- T + 1 => X"68", -- h + 2 => X"65", -- e + 3 => X"20", -- + 4 => X"44", -- D + 5 => X"72", -- r + 6 => X"65", -- e + 7 => X"61", -- a + 8 => X"6D", -- m + 9 => X"20", -- + 10 => X"54", -- T + 11 => X"65", -- e + 12 => X"61", -- a + 13 => X"6D", -- m + 14 => X"20", -- + 15 => X"3A", -- : + -- 2eme ligne (de 15 caracteres) + 16 => X"43", -- C + 17 => X"6F", -- o + 18 => X"72", -- r + 19 => X"69", -- i + 20 => X"6E", -- n + 21 => X"6E", -- n + 22 => X"65", -- e + 23 => X"20", -- + 24 => X"65", -- e + 25 => X"74", -- t + 26 => X"20", -- + 27 => X"41", -- A + 28 => X"6E", -- n + 29 => X"6E", -- n + 30 => X"65", -- e + 31 => X"21" -- ! + -- ne plus rien modifier en dessous de cette ligne + ); +begin + do <= mes(to_integer(unsigned(adr))); +end architecture; \ No newline at end of file -- cgit v1.2.3