From e170ee1dd323f3f99e154bd5daf026fc8f423465 Mon Sep 17 00:00:00 2001
From: Pacien TRAN-GIRARD
Date: Mon, 16 Jun 2014 00:04:05 +0200
Subject: Refactoring

---
 FPGA/vhdl/message.vhd     |  2 +-
 FPGA/vhdl/message.vhd.bak | 71 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 FPGA/vhdl/message.vhd.bak

(limited to 'FPGA/vhdl')

diff --git a/FPGA/vhdl/message.vhd b/FPGA/vhdl/message.vhd
index b8bccf1..9646bfe 100644
--- a/FPGA/vhdl/message.vhd
+++ b/FPGA/vhdl/message.vhd
@@ -58,7 +58,7 @@ architecture RTL of message is
 	23 => X"21",  -- ! 
 	24 => X"20",  --  
 	25 => X"20",  --  
-	26 => X"60",  --  _
+	26 => X"60",  --  \
 	27 => X"5F",  --  _
 	28 => X"5F",  --  _
 	29 => X"2F",  --  /
diff --git a/FPGA/vhdl/message.vhd.bak b/FPGA/vhdl/message.vhd.bak
new file mode 100644
index 0000000..b8bccf1
--- /dev/null
+++ b/FPGA/vhdl/message.vhd.bak
@@ -0,0 +1,71 @@
+------------------------------------------
+-- Message 32 characteres ASCII
+-- ESIEE, JPO 2008
+-- Bienvenue
+------------------------------------------
+-- Creation     : A. Exertier, mars 2008
+-- Modification : A. Exertier, avril 2013
+------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity message is
+port (
+	adr : in std_logic_vector(4 downto 0);
+	do : out std_logic_vector(7 downto 0)
+	);
+end entity;
+
+architecture RTL of message is
+  type contenu is array (0 to 31) of std_logic_vector(7 downto 0);
+  constant mes : contenu := (
+  -- 1ere ligne (de 15 caracteres)
+  -- Mettre le code ASCII (en hexadecimal) de chaque caractère
+  -- exemple T => 54 (en hexadecimal)
+  -- 0=> X"54", indique que le 1er caractere (n°0) est un T
+  -- Modifier les valeurs ASCII ci-dessous
+  
+  -- 53 63 69 65 6e 63 65 20 69 73 20 66 75 6e 21
+  -- Science is fun!
+  
+	0  => X"20",  --  
+	1  => X"53",  --  S
+	2  => X"63",  --  c
+	3  => X"69",  --  i
+	4  => X"65",  --  e
+	5  => X"6e",  --  n
+	6  => X"63",  --  c
+	7  => X"65",  --  e
+	8  => X"20",  --
+	9  => X"20",  --
+	10 => X"5E",  --  ^
+	11 => X"20",  --  
+	12 => X"20",  --  
+	13 => X"5E",  --  ^
+	14 => X"20",  --  
+	15 => X"20",  --  
+  -- 2eme ligne (de 15 caracteres)
+	16 => X"20",   --  
+	17 => X"69",  -- i
+	18 => X"73",  -- s
+	19 => X"20",  --  
+	20 => X"66",  -- f
+	21 => X"75",  -- u
+	22 => X"6e",  -- n
+	23 => X"21",  -- ! 
+	24 => X"20",  --  
+	25 => X"20",  --  
+	26 => X"60",  --  _
+	27 => X"5F",  --  _
+	28 => X"5F",  --  _
+	29 => X"2F",  --  /
+	30 => X"20",  --   
+	31 => X"20"   --  
+  -- ne plus rien modifier en dessous de cette ligne
+	);
+begin
+  do <= mes(to_integer(unsigned(adr)));
+end architecture;
\ No newline at end of file
-- 
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