From 70318492f3472ff2ec3b1735cf69a4eef1f6a51d Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Fri, 13 Jun 2014 16:06:19 +0200 Subject: Update project --- FPGA/LCD_message/LCD_controller.bsf | 141 +++++ FPGA/LCD_message/LCD_message.qpf | 30 + FPGA/LCD_message/LCD_message.qsf | 157 +++++ FPGA/LCD_message/LCD_message.qws | Bin 0 -> 1442 bytes FPGA/LCD_message/lcd.bsf | 154 +++++ FPGA/LCD_message/lcd_message.bsf | 85 +++ FPGA/LCD_message/message.bsf | 43 ++ FPGA/bind_all.tcl | 91 +++ FPGA/codec_clock/clock_divider.bsf | 61 ++ FPGA/codec_clock/codec_clock.bdf | 112 ++++ FPGA/codec_clock/codec_clock.bsf | 50 ++ FPGA/codec_clock/codec_clock.qpf | 30 + FPGA/codec_clock/codec_clock.qsf | 78 +++ FPGA/codec_clock/codec_clock.qws | Bin 0 -> 2276 bytes FPGA/commande/commande_pin.tcl.bak | 17 - FPGA/display/clock_divider.bsf | 61 ++ FPGA/display/display.bdf | 369 +++++++++-- FPGA/display/display.bsf | 83 ++- FPGA/display/display.qsf | 7 + FPGA/display/display.qws | Bin 1438 -> 1438 bytes FPGA/display/greybox_tmp/cbx_args.txt | 7 + FPGA/display/lpm_constant7nada.bsf | 49 ++ FPGA/display/lpm_constant7nada.cmp | 21 + FPGA/display/lpm_constant7nada.qip | 5 + FPGA/display/lpm_constant7nada.vhd | 109 ++++ FPGA/display/lpm_constant_a.bsf | 10 +- FPGA/display/lpm_constant_a.qip | 5 + FPGA/display/lpm_constant_a.vhd | 2 +- FPGA/display/lpm_constant_f.qip | 0 FPGA/display/lpm_counter0.qip | 0 FPGA/display/lpm_shiftreg0.bsf | 86 +++ FPGA/display/lpm_shiftreg0.cmp | 26 + FPGA/display/lpm_shiftreg0.qip | 5 + FPGA/display/lpm_shiftreg0.vhd | 146 +++++ FPGA/display/useless.bdf | 968 ++++++++++++++++++++++++++++ FPGA/display/useless.bsf | 71 +++ FPGA/pwm.tcl | 6 + FPGA/pwm/greybox_tmp/cbx_args.txt | 7 + FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v | 52 ++ FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v | 51 ++ FPGA/pwm/lpm_compare0.bsf | 62 ++ FPGA/pwm/lpm_compare0.cmp | 23 + FPGA/pwm/lpm_compare0.qip | 5 + FPGA/pwm/lpm_compare0.vhd | 126 ++++ FPGA/pwm/lpm_constant0.bsf | 49 ++ FPGA/pwm/lpm_constant0.cmp | 21 + FPGA/pwm/lpm_constant0.qip | 5 + FPGA/pwm/lpm_constant0.vhd | 109 ++++ FPGA/pwm/lpm_constant1.bsf | 49 ++ FPGA/pwm/lpm_constant1.cmp | 21 + FPGA/pwm/lpm_constant1.qip | 5 + FPGA/pwm/lpm_constant1.vhd | 109 ++++ FPGA/pwm/lpm_constant2.bsf | 49 ++ FPGA/pwm/lpm_constant2.cmp | 21 + FPGA/pwm/lpm_constant2.qip | 5 + FPGA/pwm/lpm_constant2.vhd | 109 ++++ FPGA/pwm/lpm_constant3.bsf | 49 ++ FPGA/pwm/lpm_constant3.cmp | 21 + FPGA/pwm/lpm_constant3.qip | 5 + FPGA/pwm/lpm_constant3.vhd | 109 ++++ FPGA/pwm/lpm_counter0.bsf | 64 ++ FPGA/pwm/lpm_counter0.cmp | 23 + FPGA/pwm/lpm_counter0.qip | 5 + FPGA/pwm/lpm_counter0.vhd | 130 ++++ FPGA/pwm/lpm_counter1.bsf | 65 ++ FPGA/pwm/lpm_counter1.cmp | 23 + FPGA/pwm/lpm_counter1.qip | 5 + FPGA/pwm/lpm_counter1.vhd | 133 ++++ FPGA/pwm/lpm_mux0.bsf | 82 +++ FPGA/pwm/lpm_mux0.cmp | 26 + FPGA/pwm/lpm_mux0.qip | 5 + FPGA/pwm/lpm_mux0.vhd | 210 +++++++ FPGA/pwm/pwm.bdf | 502 +++++++++++++++ FPGA/pwm/pwm.bsf | 64 ++ FPGA/pwm/pwm.qpf | 30 + FPGA/pwm/pwm.qsf | 71 +++ FPGA/pwm/pwm.qws | Bin 0 -> 1406 bytes FPGA/pwm/pwm.tcl | 6 + FPGA/sound_gene/clock_divider.bsf | 61 ++ FPGA/sound_gene/codec_clock.bsf | 50 ++ FPGA/sound_gene/codec_config.bsf | 75 +++ FPGA/sound_gene/codec_dac.bsf | 113 ++++ FPGA/sound_gene/dds_sinus.bsf | 68 ++ FPGA/sound_gene/sound_gene.bdf | 927 +++++++++++++++++++++++++++ FPGA/sound_gene/sound_gene.bsf | 113 ++++ FPGA/sound_gene/sound_gene.qpf | 30 + FPGA/sound_gene/sound_gene.qsf | 85 +++ FPGA/sound_gene/sound_gene.qws | Bin 0 -> 897 bytes FPGA/top/LCD_controller.bsf | 141 +++++ FPGA/top/clock_divider.bsf | 61 ++ FPGA/top/codec_clock.bsf | 50 ++ FPGA/top/codec_clock.qsf | 78 +++ FPGA/top/codec_config.bsf | 75 +++ FPGA/top/codec_dac.bsf | 113 ++++ FPGA/top/dds_sinus.bsf | 68 ++ FPGA/top/display.bsf | 83 ++- FPGA/top/greybox_tmp/cbx_args.txt | 9 + FPGA/top/lcd_message.bsf | 85 +++ FPGA/top/lpm_compare0.bsf | 62 ++ FPGA/top/lpm_counter0.bsf | 64 ++ FPGA/top/lpm_counter1.bsf | 65 ++ FPGA/top/lpm_counter1.qip | 0 FPGA/top/lpm_mux0.bsf | 82 +++ FPGA/top/message.bsf | 43 ++ FPGA/top/pwm.bsf | 64 ++ FPGA/top/sound_gene.bsf | 113 ++++ FPGA/top/top.bdf | 1015 ++++++++++++++++++++++++++---- FPGA/top/top.bsf | 232 +++++++ FPGA/top/top.qsf | 57 +- FPGA/top/top.tcl | 212 +++++++ FPGA/top/useless.bsf | 71 +++ FPGA/vhdl/LCD_message.bdf | 415 ++++++++++++ FPGA/vhdl/codec_config.vhd | 21 +- FPGA/vhdl/dds_sinus.vhd | 4 +- FPGA/vhdl/greybox_tmp/cbx_args.txt | 12 + FPGA/vhdl/i2c_master.vhd | 526 ++++++++-------- FPGA/vhdl/lpm_shiftreg0.qip | 0 FPGA/vhdl/message.vhd | 66 +- FPGA/vhdl/message.vhd.bak | 67 ++ 119 files changed, 10533 insertions(+), 534 deletions(-) create mode 100644 FPGA/LCD_message/LCD_controller.bsf create mode 100644 FPGA/LCD_message/LCD_message.qpf create mode 100644 FPGA/LCD_message/LCD_message.qsf create mode 100644 FPGA/LCD_message/LCD_message.qws create mode 100644 FPGA/LCD_message/lcd.bsf create mode 100644 FPGA/LCD_message/lcd_message.bsf create mode 100644 FPGA/LCD_message/message.bsf create mode 100644 FPGA/bind_all.tcl create mode 100644 FPGA/codec_clock/clock_divider.bsf create mode 100644 FPGA/codec_clock/codec_clock.bdf create mode 100644 FPGA/codec_clock/codec_clock.bsf create mode 100644 FPGA/codec_clock/codec_clock.qpf create mode 100644 FPGA/codec_clock/codec_clock.qsf create mode 100644 FPGA/codec_clock/codec_clock.qws delete mode 100644 FPGA/commande/commande_pin.tcl.bak create mode 100644 FPGA/display/clock_divider.bsf create mode 100644 FPGA/display/greybox_tmp/cbx_args.txt create mode 100644 FPGA/display/lpm_constant7nada.bsf create mode 100644 FPGA/display/lpm_constant7nada.cmp create mode 100644 FPGA/display/lpm_constant7nada.qip create mode 100644 FPGA/display/lpm_constant7nada.vhd create mode 100644 FPGA/display/lpm_constant_a.qip create mode 100644 FPGA/display/lpm_constant_f.qip create mode 100644 FPGA/display/lpm_counter0.qip create mode 100644 FPGA/display/lpm_shiftreg0.bsf create mode 100644 FPGA/display/lpm_shiftreg0.cmp create mode 100644 FPGA/display/lpm_shiftreg0.qip create mode 100644 FPGA/display/lpm_shiftreg0.vhd create mode 100644 FPGA/display/useless.bdf create mode 100644 FPGA/display/useless.bsf create mode 100644 FPGA/pwm.tcl create mode 100644 FPGA/pwm/greybox_tmp/cbx_args.txt create mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v create mode 100644 FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v create mode 100644 FPGA/pwm/lpm_compare0.bsf create mode 100644 FPGA/pwm/lpm_compare0.cmp create mode 100644 FPGA/pwm/lpm_compare0.qip create mode 100644 FPGA/pwm/lpm_compare0.vhd create mode 100644 FPGA/pwm/lpm_constant0.bsf create mode 100644 FPGA/pwm/lpm_constant0.cmp create mode 100644 FPGA/pwm/lpm_constant0.qip create mode 100644 FPGA/pwm/lpm_constant0.vhd create mode 100644 FPGA/pwm/lpm_constant1.bsf create mode 100644 FPGA/pwm/lpm_constant1.cmp create mode 100644 FPGA/pwm/lpm_constant1.qip create mode 100644 FPGA/pwm/lpm_constant1.vhd create mode 100644 FPGA/pwm/lpm_constant2.bsf create mode 100644 FPGA/pwm/lpm_constant2.cmp create mode 100644 FPGA/pwm/lpm_constant2.qip create mode 100644 FPGA/pwm/lpm_constant2.vhd create mode 100644 FPGA/pwm/lpm_constant3.bsf create mode 100644 FPGA/pwm/lpm_constant3.cmp create mode 100644 FPGA/pwm/lpm_constant3.qip create mode 100644 FPGA/pwm/lpm_constant3.vhd create mode 100644 FPGA/pwm/lpm_counter0.bsf create mode 100644 FPGA/pwm/lpm_counter0.cmp create mode 100644 FPGA/pwm/lpm_counter0.qip create mode 100644 FPGA/pwm/lpm_counter0.vhd create mode 100644 FPGA/pwm/lpm_counter1.bsf create mode 100644 FPGA/pwm/lpm_counter1.cmp create mode 100644 FPGA/pwm/lpm_counter1.qip create mode 100644 FPGA/pwm/lpm_counter1.vhd create mode 100644 FPGA/pwm/lpm_mux0.bsf create mode 100644 FPGA/pwm/lpm_mux0.cmp create mode 100644 FPGA/pwm/lpm_mux0.qip create mode 100644 FPGA/pwm/lpm_mux0.vhd create mode 100644 FPGA/pwm/pwm.bdf create mode 100644 FPGA/pwm/pwm.bsf create mode 100644 FPGA/pwm/pwm.qpf create mode 100644 FPGA/pwm/pwm.qsf create mode 100644 FPGA/pwm/pwm.qws create mode 100644 FPGA/pwm/pwm.tcl create mode 100644 FPGA/sound_gene/clock_divider.bsf create mode 100644 FPGA/sound_gene/codec_clock.bsf create mode 100644 FPGA/sound_gene/codec_config.bsf create mode 100644 FPGA/sound_gene/codec_dac.bsf create mode 100644 FPGA/sound_gene/dds_sinus.bsf create mode 100644 FPGA/sound_gene/sound_gene.bdf create mode 100644 FPGA/sound_gene/sound_gene.bsf create mode 100644 FPGA/sound_gene/sound_gene.qpf create mode 100644 FPGA/sound_gene/sound_gene.qsf create mode 100644 FPGA/sound_gene/sound_gene.qws create mode 100644 FPGA/top/LCD_controller.bsf create mode 100644 FPGA/top/clock_divider.bsf create mode 100644 FPGA/top/codec_clock.bsf create mode 100644 FPGA/top/codec_clock.qsf create mode 100644 FPGA/top/codec_config.bsf create mode 100644 FPGA/top/codec_dac.bsf create mode 100644 FPGA/top/dds_sinus.bsf create mode 100644 FPGA/top/greybox_tmp/cbx_args.txt create mode 100644 FPGA/top/lcd_message.bsf create mode 100644 FPGA/top/lpm_compare0.bsf create mode 100644 FPGA/top/lpm_counter0.bsf create mode 100644 FPGA/top/lpm_counter1.bsf create mode 100644 FPGA/top/lpm_counter1.qip create mode 100644 FPGA/top/lpm_mux0.bsf create mode 100644 FPGA/top/message.bsf create mode 100644 FPGA/top/pwm.bsf create mode 100644 FPGA/top/sound_gene.bsf create mode 100644 FPGA/top/top.bsf create mode 100644 FPGA/top/top.tcl create mode 100644 FPGA/top/useless.bsf create mode 100644 FPGA/vhdl/LCD_message.bdf create mode 100644 FPGA/vhdl/greybox_tmp/cbx_args.txt create mode 100644 FPGA/vhdl/lpm_shiftreg0.qip create mode 100644 FPGA/vhdl/message.vhd.bak (limited to 'FPGA') diff --git a/FPGA/LCD_message/LCD_controller.bsf b/FPGA/LCD_message/LCD_controller.bsf new file mode 100644 index 0000000..9f6a194 --- /dev/null +++ b/FPGA/LCD_message/LCD_controller.bsf @@ -0,0 +1,141 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 232 256) + (text "LCD_controller" (rect 5 0 66 12)(font "Arial" )) + (text "inst" (rect 8 224 20 236)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "en_250kHz" (rect 0 0 44 12)(font "Arial" )) + (text "en_250kHz" (rect 21 59 65 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "mode[1..0]" (rect 0 0 41 12)(font "Arial" )) + (text "mode[1..0]" (rect 21 75 62 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 0 96) + (input) + (text "char[7..0]" (rect 0 0 37 12)(font "Arial" )) + (text "char[7..0]" (rect 21 91 58 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address[6..0]" (rect 0 0 51 12)(font "Arial" )) + (text "address[6..0]" (rect 21 107 72 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "write_char" (rect 0 0 41 12)(font "Arial" )) + (text "write_char" (rect 21 123 62 135)(font "Arial" )) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "write_address" (rect 0 0 55 12)(font "Arial" )) + (text "write_address" (rect 21 139 76 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "D" (rect 0 0 7 12)(font "Arial" )) + (text "D" (rect 21 155 28 167)(font "Arial" )) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "C" (rect 0 0 7 12)(font "Arial" )) + (text "C" (rect 21 171 28 183)(font "Arial" )) + (line (pt 0 176)(pt 16 176)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "B" (rect 0 0 5 12)(font "Arial" )) + (text "B" (rect 21 187 26 199)(font "Arial" )) + (line (pt 0 192)(pt 16 192)(line_width 1)) + ) + (port + (pt 216 32) + (output) + (text "ready" (rect 0 0 23 12)(font "Arial" )) + (text "ready" (rect 172 27 195 39)(font "Arial" )) + (line (pt 216 32)(pt 200 32)(line_width 1)) + ) + (port + (pt 216 64) + (output) + (text "LCD_RS" (rect 0 0 40 12)(font "Arial" )) + (text "LCD_RS" (rect 155 59 195 71)(font "Arial" )) + (line (pt 216 64)(pt 200 64)(line_width 1)) + ) + (port + (pt 216 80) + (output) + (text "LCD_RW" (rect 0 0 44 12)(font "Arial" )) + (text "LCD_RW" (rect 151 75 195 87)(font "Arial" )) + (line (pt 216 80)(pt 200 80)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "LCD_EN" (rect 0 0 40 12)(font "Arial" )) + (text "LCD_EN" (rect 155 91 195 103)(font "Arial" )) + (line (pt 216 96)(pt 200 96)(line_width 1)) + ) + (port + (pt 216 48) + (bidir) + (text "LCD_data[7..0]" (rect 0 0 62 12)(font "Arial" )) + (text "LCD_data[7..0]" (rect 133 43 195 55)(font "Arial" )) + (line (pt 216 48)(pt 200 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 224)(line_width 1)) + ) +) diff --git a/FPGA/LCD_message/LCD_message.qpf b/FPGA/LCD_message/LCD_message.qpf new file mode 100644 index 0000000..fd5d9af --- /dev/null +++ b/FPGA/LCD_message/LCD_message.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:35:48 juin 02, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:35:48 juin 02, 2014" + +# Revisions + +PROJECT_REVISION = "LCD_message" diff --git a/FPGA/LCD_message/LCD_message.qsf b/FPGA/LCD_message/LCD_message.qsf new file mode 100644 index 0000000..600b941 --- /dev/null +++ b/FPGA/LCD_message/LCD_message.qsf @@ -0,0 +1,157 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:35:48 juin 02, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# LCD_message_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY LCD_message +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:35:48 JUIN 02, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE ../vhdl/seven_segment_decoder.vhd +set_global_assignment -name VHDL_FILE ../vhdl/rom_sinus.vhd +set_global_assignment -name VHDL_FILE ../vhdl/i2c_master.vhd +set_global_assignment -name VHDL_FILE ../vhdl/dds_sinus.vhd +set_global_assignment -name VHDL_FILE ../vhdl/codec_dac.vhd +set_global_assignment -name VHDL_FILE ../vhdl/codec_config.vhd +set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd +set_global_assignment -name VHDL_FILE ../vhdl/message.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd_message.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd_controller.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name BDF_FILE ../vhdl/LCD_message.bdf +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_AE23 -to alarm +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_M23 -to hot +set_location_assignment PIN_K26 -to fan +set_location_assignment PIN_B4 -to aud_bclk +set_location_assignment PIN_A4 -to aud_dacdat +set_location_assignment PIN_C6 -to aud_daclrck +set_location_assignment PIN_A5 -to aud_xck +set_location_assignment PIN_A6 -to i2c_sclk +set_location_assignment PIN_B6 -to i2c_sdat +set_location_assignment PIN_M20 -to sound_high_level +set_location_assignment PIN_Y18 -to led_fan +set_location_assignment PIN_AE22 -to end_config +set_location_assignment PIN_M25 -to xti_mclk +set_location_assignment PIN_K1 -to LCD_RS +set_location_assignment PIN_K4 -to LCD_RW +set_location_assignment PIN_K3 -to LCD_EN +set_location_assignment PIN_K2 -to LCD_BLON +set_location_assignment PIN_L4 -to LCD_ON +set_location_assignment PIN_H3 -to LCD_DATA[7] +set_location_assignment PIN_H4 -to LCD_DATA[6] +set_location_assignment PIN_J3 -to LCD_DATA[5] +set_location_assignment PIN_J4 -to LCD_DATA[4] +set_location_assignment PIN_H2 -to LCD_DATA[3] +set_location_assignment PIN_H1 -to LCD_DATA[2] +set_location_assignment PIN_J2 -to LCD_DATA[1] +set_location_assignment PIN_J1 -to LCD_DATA[0] +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] \ No newline at end of file diff --git a/FPGA/LCD_message/LCD_message.qws b/FPGA/LCD_message/LCD_message.qws new file mode 100644 index 0000000..8caa39c Binary files /dev/null and b/FPGA/LCD_message/LCD_message.qws differ diff --git a/FPGA/LCD_message/lcd.bsf b/FPGA/LCD_message/lcd.bsf new file mode 100644 index 0000000..a47d0f6 --- /dev/null +++ b/FPGA/LCD_message/lcd.bsf @@ -0,0 +1,154 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 224 224) + (text "lcd" (rect 5 0 15 12)(font "Arial" )) + (text "inst" (rect 8 192 20 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "mode[1..0]" (rect 0 0 41 12)(font "Arial" )) + (text "mode[1..0]" (rect 21 59 62 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "char[7..0]" (rect 0 0 37 12)(font "Arial" )) + (text "char[7..0]" (rect 21 75 58 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 0 96) + (input) + (text "address[6..0]" (rect 0 0 51 12)(font "Arial" )) + (text "address[6..0]" (rect 21 91 72 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "write_char" (rect 0 0 41 12)(font "Arial" )) + (text "write_char" (rect 21 107 62 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "write_address" (rect 0 0 55 12)(font "Arial" )) + (text "write_address" (rect 21 123 76 135)(font "Arial" )) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "D" (rect 0 0 7 12)(font "Arial" )) + (text "D" (rect 21 139 28 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "C" (rect 0 0 7 12)(font "Arial" )) + (text "C" (rect 21 155 28 167)(font "Arial" )) + (line (pt 0 160)(pt 16 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "B" (rect 0 0 5 12)(font "Arial" )) + (text "B" (rect 21 171 26 183)(font "Arial" )) + (line (pt 0 176)(pt 16 176)(line_width 1)) + ) + (port + (pt 208 32) + (output) + (text "ready" (rect 0 0 23 12)(font "Arial" )) + (text "ready" (rect 164 27 187 39)(font "Arial" )) + (line (pt 208 32)(pt 192 32)(line_width 1)) + ) + (port + (pt 208 64) + (output) + (text "lcd_on" (rect 0 0 25 12)(font "Arial" )) + (text "lcd_on" (rect 162 59 187 71)(font "Arial" )) + (line (pt 208 64)(pt 192 64)(line_width 1)) + ) + (port + (pt 208 80) + (output) + (text "lcd_blon" (rect 0 0 31 12)(font "Arial" )) + (text "lcd_blon" (rect 156 75 187 87)(font "Arial" )) + (line (pt 208 80)(pt 192 80)(line_width 1)) + ) + (port + (pt 208 96) + (output) + (text "lcd_rs" (rect 0 0 24 12)(font "Arial" )) + (text "lcd_rs" (rect 163 91 187 103)(font "Arial" )) + (line (pt 208 96)(pt 192 96)(line_width 1)) + ) + (port + (pt 208 112) + (output) + (text "lcd_rw" (rect 0 0 25 12)(font "Arial" )) + (text "lcd_rw" (rect 162 107 187 119)(font "Arial" )) + (line (pt 208 112)(pt 192 112)(line_width 1)) + ) + (port + (pt 208 128) + (output) + (text "lcd_en" (rect 0 0 25 12)(font "Arial" )) + (text "lcd_en" (rect 162 123 187 135)(font "Arial" )) + (line (pt 208 128)(pt 192 128)(line_width 1)) + ) + (port + (pt 208 48) + (bidir) + (text "lcd_data[7..0]" (rect 0 0 53 12)(font "Arial" )) + (text "lcd_data[7..0]" (rect 134 43 187 55)(font "Arial" )) + (line (pt 208 48)(pt 192 48)(line_width 3)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 192 192)(line_width 1)) + ) + (annotation_block (parameter)(rect 224 -64 324 16)) +) diff --git a/FPGA/LCD_message/lcd_message.bsf b/FPGA/LCD_message/lcd_message.bsf new file mode 100644 index 0000000..946183f --- /dev/null +++ b/FPGA/LCD_message/lcd_message.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 216 160) + (text "lcd_message" (rect 5 0 58 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 200 48) + (output) + (text "LCD_ON" (rect 0 0 40 12)(font "Arial" )) + (text "LCD_ON" (rect 139 43 179 55)(font "Arial" )) + (line (pt 200 48)(pt 184 48)(line_width 1)) + ) + (port + (pt 200 64) + (output) + (text "LCD_BLON" (rect 0 0 51 12)(font "Arial" )) + (text "LCD_BLON" (rect 128 59 179 71)(font "Arial" )) + (line (pt 200 64)(pt 184 64)(line_width 1)) + ) + (port + (pt 200 80) + (output) + (text "LCD_RS" (rect 0 0 40 12)(font "Arial" )) + (text "LCD_RS" (rect 139 75 179 87)(font "Arial" )) + (line (pt 200 80)(pt 184 80)(line_width 1)) + ) + (port + (pt 200 96) + (output) + (text "LCD_RW" (rect 0 0 44 12)(font "Arial" )) + (text "LCD_RW" (rect 135 91 179 103)(font "Arial" )) + (line (pt 200 96)(pt 184 96)(line_width 1)) + ) + (port + (pt 200 112) + (output) + (text "LCD_EN" (rect 0 0 40 12)(font "Arial" )) + (text "LCD_EN" (rect 139 107 179 119)(font "Arial" )) + (line (pt 200 112)(pt 184 112)(line_width 1)) + ) + (port + (pt 200 32) + (bidir) + (text "LCD_DATA[7..0]" (rect 0 0 75 12)(font "Arial" )) + (text "LCD_DATA[7..0]" (rect 104 27 179 39)(font "Arial" )) + (line (pt 200 32)(pt 184 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 184 128)(line_width 1)) + ) +) diff --git a/FPGA/LCD_message/message.bsf b/FPGA/LCD_message/message.bsf new file mode 100644 index 0000000..9e08aba --- /dev/null +++ b/FPGA/LCD_message/message.bsf @@ -0,0 +1,43 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 184 96) + (text "message" (rect 5 0 41 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "adr[4..0]" (rect 0 0 34 12)(font "Arial" )) + (text "adr[4..0]" (rect 21 27 55 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 168 32) + (output) + (text "do[7..0]" (rect 0 0 29 12)(font "Arial" )) + (text "do[7..0]" (rect 118 27 147 39)(font "Arial" )) + (line (pt 168 32)(pt 152 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 152 64)(line_width 1)) + ) +) diff --git a/FPGA/bind_all.tcl b/FPGA/bind_all.tcl new file mode 100644 index 0000000..34d37c2 --- /dev/null +++ b/FPGA/bind_all.tcl @@ -0,0 +1,91 @@ +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_AE23 -to alarm +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_M23 -to hot +set_location_assignment PIN_K26 -to fan +set_location_assignment PIN_B4 -to aud_bclk +set_location_assignment PIN_A4 -to aud_dacdat +set_location_assignment PIN_C6 -to aud_daclrck +set_location_assignment PIN_A5 -to aud_xck +set_location_assignment PIN_A6 -to i2c_sclk +set_location_assignment PIN_B6 -to i2c_sdat +set_location_assignment PIN_M20 -to sound_high_level +set_location_assignment PIN_Y18 -to led_fan +set_location_assignment PIN_AE22 -to end_config +set_location_assignment PIN_M25 -to xti_mclk +set_location_assignment PIN_K1 -to LCD_RS +set_location_assignment PIN_K4 -to LCD_RW +set_location_assignment PIN_K3 -to LCD_EN +set_location_assignment PIN_K2 -to LCD_BLON +set_location_assignment PIN_L4 -to LCD_ON +set_location_assignment PIN_H3 -to LCD_DATA[7] +set_location_assignment PIN_H4 -to LCD_DATA[6] +set_location_assignment PIN_J3 -to LCD_DATA[5] +set_location_assignment PIN_J4 -to LCD_DATA[4] +set_location_assignment PIN_H2 -to LCD_DATA[3] +set_location_assignment PIN_H1 -to LCD_DATA[2] +set_location_assignment PIN_J2 -to LCD_DATA[1] +set_location_assignment PIN_J1 -to LCD_DATA[0] +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] diff --git a/FPGA/codec_clock/clock_divider.bsf b/FPGA/codec_clock/clock_divider.bsf new file mode 100644 index 0000000..de8cb37 --- /dev/null +++ b/FPGA/codec_clock/clock_divider.bsf @@ -0,0 +1,61 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 96) + (text "clock_divider" (rect 5 0 56 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "en_user" (rect 0 0 33 12)(font "Arial" )) + (text "en_user" (rect 106 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 1)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (parameter + "user_frequency" + "4.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 144 64)(line_width 1)) + ) + (annotation_block (parameter)(rect 176 -64 276 16)) +) diff --git a/FPGA/codec_clock/codec_clock.bdf b/FPGA/codec_clock/codec_clock.bdf new file mode 100644 index 0000000..df9857d --- /dev/null +++ b/FPGA/codec_clock/codec_clock.bdf @@ -0,0 +1,112 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 128 104 296 120) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 21 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 72 120 128 136)) +) +(pin + (input) + (rect 128 120 296 136) + (text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6))) + (text "resetn" (rect 5 0 37 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 149 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 64 136 128 152)) +) +(pin + (output) + (rect 456 104 632 120) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "xti_mclk" (rect 90 0 131 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 632 120 696 136)) +) +(symbol + (rect 296 80 456 160) + (text "clock_divider" (rect 5 0 71 11)(font "Arial" )) + (text "inst" (rect 8 64 26 75)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 15 11)(font "Arial" )) + (text "clk" (rect 21 27 36 38)(font "Arial" )) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 31 11)(font "Arial" )) + (text "resetn" (rect 21 43 52 54)(font "Arial" )) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 160 32) + (output) + (text "en_user" (rect 0 0 42 11)(font "Arial" )) + (text "en_user" (rect 104 27 146 38)(font "Arial" )) + (line (pt 160 32)(pt 144 32)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (parameter + "user_frequency" + "16666666.6" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 144 64)) + ) + (annotation_block (parameter)(rect 456 40 641 79)) +) diff --git a/FPGA/codec_clock/codec_clock.bsf b/FPGA/codec_clock/codec_clock.bsf new file mode 100644 index 0000000..c112470 --- /dev/null +++ b/FPGA/codec_clock/codec_clock.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 152 112) + (text "codec_clock" (rect 5 0 76 13)(font "Arial" (font_size 8))) + (text "inst" (rect 8 81 26 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8))) + (text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 136 32) + (output) + (text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8))) + (text "xti_mclk" (rect 67 27 115 40)(font "Arial" (font_size 8))) + (line (pt 136 32)(pt 120 32)) + ) + (drawing + (rectangle (rect 16 16 120 80)) + ) +) diff --git a/FPGA/codec_clock/codec_clock.qpf b/FPGA/codec_clock/codec_clock.qpf new file mode 100644 index 0000000..0dac0d9 --- /dev/null +++ b/FPGA/codec_clock/codec_clock.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:18:56 mai 26, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "15:18:56 mai 26, 2014" + +# Revisions + +PROJECT_REVISION = "codec_clock" diff --git a/FPGA/codec_clock/codec_clock.qsf b/FPGA/codec_clock/codec_clock.qsf new file mode 100644 index 0000000..c11cd5a --- /dev/null +++ b/FPGA/codec_clock/codec_clock.qsf @@ -0,0 +1,78 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 15:18:56 mai 26, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# codec_clock_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY codec_clock +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:18:56 MAI 26, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd +set_global_assignment -name BDF_FILE codec_clock.bdf +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_AE23 -to alarm +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_M23 -to hot +set_location_assignment PIN_K26 -to fan +set_location_assignment PIN_B4 -to aud_bclk +set_location_assignment PIN_A4 -to aud_dacdat +set_location_assignment PIN_C6 -to aud_daclrck +set_location_assignment PIN_A5 -to aud_xck +set_location_assignment PIN_A6 -to i2c_sclk +set_location_assignment PIN_B6 -to i2c_sdat +set_location_assignment PIN_M20 -to sound_high_level +set_location_assignment PIN_Y18 -to led_fan +set_location_assignment PIN_AE22 -to end_config +set_location_assignment PIN_M25 -to xti_mclk +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA/codec_clock/codec_clock.qws b/FPGA/codec_clock/codec_clock.qws new file mode 100644 index 0000000..b64e61b Binary files /dev/null and b/FPGA/codec_clock/codec_clock.qws differ diff --git a/FPGA/commande/commande_pin.tcl.bak b/FPGA/commande/commande_pin.tcl.bak deleted file mode 100644 index 7b34d44..0000000 --- a/FPGA/commande/commande_pin.tcl.bak +++ /dev/null @@ -1,17 +0,0 @@ -set_location_assignment PIN_N2 -to clk -set_location_assignment PIN_G26 -to resetn - -set_location_assignment PIN_AE14 -to speed_user[1] -set_location_assignment PIN_AF14 -to speed_user[0] - -set_location_assignment PIN_N26 -to fan_auto_user -set_location_assignment PIN_N25 -to alarm_user - -set_location_assignment PIN_V2 -to hot -set_location_assignment PIN_V1 -to sound_high_level - -set_location_assignment PIN_AC22 -to speed[1] -set_location_assignment PIN_AB21 -to speed[0] - -set_location_assignment PIN_AF23 -to fan_auto -set_location_assignment PIN_AE23 -to alarm \ No newline at end of file diff --git a/FPGA/display/clock_divider.bsf b/FPGA/display/clock_divider.bsf new file mode 100644 index 0000000..de8cb37 --- /dev/null +++ b/FPGA/display/clock_divider.bsf @@ -0,0 +1,61 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 176 96) + (text "clock_divider" (rect 5 0 56 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 24 12)(font "Arial" )) + (text "resetn" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "en_user" (rect 0 0 33 12)(font "Arial" )) + (text "en_user" (rect 106 27 139 39)(font "Arial" )) + (line (pt 160 32)(pt 144 32)(line_width 1)) + ) + (parameter + "board_frequency" + "50000000.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (parameter + "user_frequency" + "4.0" + "" + (type "PARAMETER_SIGNED_FLOAT") ) + (drawing + (rectangle (rect 16 16 144 64)(line_width 1)) + ) + (annotation_block (parameter)(rect 176 -64 276 16)) +) diff --git a/FPGA/display/display.bdf b/FPGA/display/display.bdf index c40e75b..fb2a670 100644 --- a/FPGA/display/display.bdf +++ b/FPGA/display/display.bdf @@ -22,8 +22,8 @@ applicable agreement for further details. (pin (input) (rect 96 48 272 64) - (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) - (text "fan_auto" (rect 9 0 52 11)(font "Arial" )) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "fan_auto" (rect 9 0 53 11)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) @@ -33,13 +33,14 @@ applicable agreement for further details. (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) - (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 32 64 96 80)) ) (pin (input) (rect 96 64 272 80) - (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) - (text "alarm_user" (rect 9 0 65 11)(font "Arial" )) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "alarm_user" (rect 9 0 66 11)(font "Arial" )) (pt 176 8) (drawing (line (pt 92 12)(pt 117 12)) @@ -49,12 +50,13 @@ applicable agreement for further details. (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) - (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 32 80 96 96)) ) (pin (input) (rect 96 80 272 96) - (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "speed[1..0]" (rect 9 0 64 11)(font "Arial" )) (pt 176 8) (drawing @@ -65,12 +67,45 @@ applicable agreement for further details. (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) - (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 24 96 96 112)) +) +(pin + (input) + (rect 104 8 280 24) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "clk" (rect 9 0 24 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 104 24 280 40) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "resetn" (rect 9 0 40 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) ) (pin (output) (rect 760 48 936 64) - (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "hex7[6..0]" (rect 90 0 138 11)(font "Arial" )) (pt 0 8) (drawing @@ -82,11 +117,12 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) + (annotation_block (location)(rect 936 64 992 80)) ) (pin (output) (rect 760 64 936 80) - (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "hex6[6..0]" (rect 90 0 138 11)(font "Arial" )) (pt 0 8) (drawing @@ -98,11 +134,12 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) + (annotation_block (location)(rect 936 80 992 96)) ) (pin (output) - (rect 760 80 936 96) - (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (rect 760 104 936 120) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "hex4[6..0]" (rect 90 0 138 11)(font "Arial" )) (pt 0 8) (drawing @@ -114,10 +151,96 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) + (annotation_block (location)(rect 936 120 992 136)) +) +(pin + (output) + (rect 760 88 936 104) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "hex5[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 936 104 992 120)) +) +(pin + (output) + (rect 760 176 936 192) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "hex0[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 936 192 1000 208)) +) +(pin + (output) + (rect 760 160 936 176) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "hex1[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 936 176 1000 192)) +) +(pin + (output) + (rect 760 144 936 160) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "hex2[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 936 160 1008 176)) +) +(pin + (output) + (rect 760 128 936 144) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "hex3[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 936 144 1000 160)) ) (symbol (rect 216 544 248 576) - (text "GND" (rect 8 16 29 26)(font "Arial" (font_size 6))) + (text "GND" (rect 8 16 30 26)(font "Arial" (font_size 6))) (text "inst1" (rect 3 21 26 32)(font "Arial" )(invisible)) (port (pt 16 0) @@ -134,8 +257,8 @@ applicable agreement for further details. ) (symbol (rect 392 496 568 576) - (text "seven_segment_decoder" (rect 5 0 130 11)(font "Arial" )) - (text "fan_speed" (rect 8 64 59 75)(font "Arial" )) + (text "seven_segment_decoder" (rect 5 0 131 11)(font "Arial" )) + (text "fan_speed" (rect 8 64 61 75)(font "Arial" )) (port (pt 0 32) (input) @@ -147,7 +270,7 @@ applicable agreement for further details. (pt 176 32) (output) (text "hex[6..0]" (rect 0 0 42 11)(font "Arial" )) - (text "hex[6..0]" (rect 120 27 155 38)(font "Arial" )) + (text "hex[6..0]" (rect 120 27 162 38)(font "Arial" )) (line (pt 176 32)(pt 160 32)(line_width 3)) ) (parameter @@ -162,8 +285,8 @@ applicable agreement for further details. ) (symbol (rect 392 624 568 704) - (text "seven_segment_decoder" (rect 5 0 130 11)(font "Arial" )) - (text "a" (rect 8 64 15 75)(font "Arial" )) + (text "seven_segment_decoder" (rect 5 0 131 11)(font "Arial" )) + (text "a" (rect 8 64 16 75)(font "Arial" )) (port (pt 0 32) (input) @@ -175,7 +298,7 @@ applicable agreement for further details. (pt 176 32) (output) (text "hex[6..0]" (rect 0 0 42 11)(font "Arial" )) - (text "hex[6..0]" (rect 120 27 155 38)(font "Arial" )) + (text "hex[6..0]" (rect 120 27 162 38)(font "Arial" )) (line (pt 176 32)(pt 160 32)(line_width 3)) ) (parameter @@ -190,8 +313,8 @@ applicable agreement for further details. ) (symbol (rect 392 752 568 832) - (text "seven_segment_decoder" (rect 5 0 130 11)(font "Arial" )) - (text "f" (rect 8 64 11 75)(font "Arial" )) + (text "seven_segment_decoder" (rect 5 0 131 11)(font "Arial" )) + (text "f" (rect 8 64 12 75)(font "Arial" )) (port (pt 0 32) (input) @@ -203,7 +326,7 @@ applicable agreement for further details. (pt 176 32) (output) (text "hex[6..0]" (rect 0 0 42 11)(font "Arial" )) - (text "hex[6..0]" (rect 120 27 155 38)(font "Arial" )) + (text "hex[6..0]" (rect 120 27 162 38)(font "Arial" )) (line (pt 176 32)(pt 160 32)(line_width 3)) ) (parameter @@ -218,34 +341,34 @@ applicable agreement for further details. ) (symbol (rect 424 320 536 408) - (text "BUSMUX" (rect 28 0 95 16)(font "Arial" (font_size 10))) - (text "inst10" (rect 3 77 37 90)(font "Arial" (font_size 8))) + (text "BUSMUX" (rect 28 0 96 16)(font "Arial" (font_size 10))) + (text "inst10" (rect 3 77 38 90)(font "Arial" (font_size 8))) (port (pt 0 64) (input) - (text "datab[WIDTH-1..0]" (rect 6 51 111 64)(font "