From d091bb2cb82f66d187df8f3aba6afcf4041b72ce Mon Sep 17 00:00:00 2001 From: Pacien TRAN-GIRARD Date: Fri, 11 Apr 2014 22:57:17 +0200 Subject: Add top module --- FPGA/display/display.bsf | 71 ++++++++ FPGA/display/display.qws | Bin 0 -> 1438 bytes FPGA/top/7seg_pin.tcl | 56 ++++++ FPGA/top/commande.bsf | 99 +++++++++++ FPGA/top/demo_io_pin.tcl | 17 ++ FPGA/top/display.bsf | 71 ++++++++ FPGA/top/lcd_pin.tcl | 13 ++ FPGA/top/real_io_pin.tcl | 22 +++ FPGA/top/top.bdf | 443 +++++++++++++++++++++++++++++++++++++++++++++++ FPGA/top/top.qpf | 30 ++++ FPGA/top/top.qsf | 161 +++++++++++++++++ 11 files changed, 983 insertions(+) create mode 100644 FPGA/display/display.bsf create mode 100644 FPGA/display/display.qws create mode 100644 FPGA/top/7seg_pin.tcl create mode 100644 FPGA/top/commande.bsf create mode 100644 FPGA/top/demo_io_pin.tcl create mode 100644 FPGA/top/display.bsf create mode 100644 FPGA/top/lcd_pin.tcl create mode 100644 FPGA/top/real_io_pin.tcl create mode 100644 FPGA/top/top.bdf create mode 100644 FPGA/top/top.qpf create mode 100644 FPGA/top/top.qsf (limited to 'FPGA') diff --git a/FPGA/display/display.bsf b/FPGA/display/display.bsf new file mode 100644 index 0000000..ed4adb7 --- /dev/null +++ b/FPGA/display/display.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 192 112) + (text "display" (rect 5 0 46 13)(font "Arial" (font_size 8))) + (text "inst" (rect 8 81 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "fan_auto" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "fan_auto" (rect 21 27 70 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "alarm_user" (rect 0 0 63 13)(font "Arial" (font_size 8))) + (text "alarm_user" (rect 21 43 84 56)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "speed[1..0]" (rect 0 0 62 13)(font "Arial" (font_size 8))) + (text "speed[1..0]" (rect 21 59 83 72)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "hex7[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex7[6..0]" (rect 100 27 155 40)(font "Arial" (font_size 8))) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (port + (pt 176 48) + (output) + (text "hex6[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex6[6..0]" (rect 100 43 155 56)(font "Arial" (font_size 8))) + (line (pt 176 48)(pt 160 48)(line_width 3)) + ) + (port + (pt 176 64) + (output) + (text "hex4[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex4[6..0]" (rect 100 59 155 72)(font "Arial" (font_size 8))) + (line (pt 176 64)(pt 160 64)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 160 80)) + ) +) diff --git a/FPGA/display/display.qws b/FPGA/display/display.qws new file mode 100644 index 0000000..4904320 Binary files /dev/null and b/FPGA/display/display.qws differ diff --git a/FPGA/top/7seg_pin.tcl b/FPGA/top/7seg_pin.tcl new file mode 100644 index 0000000..317ef52 --- /dev/null +++ b/FPGA/top/7seg_pin.tcl @@ -0,0 +1,56 @@ +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] \ No newline at end of file diff --git a/FPGA/top/commande.bsf b/FPGA/top/commande.bsf new file mode 100644 index 0000000..54f329e --- /dev/null +++ b/FPGA/top/commande.bsf @@ -0,0 +1,99 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 232 176) + (text "commande" (rect 5 0 67 13)(font "Arial" (font_size 8))) + (text "inst" (rect 8 145 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 17 13)(font "Arial" (font_size 8))) + (text "clk" (rect 21 27 38 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "resetn" (rect 0 0 35 13)(font "Arial" (font_size 8))) + (text "resetn" (rect 21 43 56 56)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "speed_user[1..0]" (rect 0 0 94 13)(font "Arial" (font_size 8))) + (text "speed_user[1..0]" (rect 21 59 115 72)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "fan_auto_user" (rect 0 0 81 13)(font "Arial" (font_size 8))) + (text "fan_auto_user" (rect 21 75 102 88)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "alarm_user" (rect 0 0 63 13)(font "Arial" (font_size 8))) + (text "alarm_user" (rect 21 91 84 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)) + ) + (port + (pt 0 112) + (input) + (text "hot" (rect 0 0 17 13)(font "Arial" (font_size 8))) + (text "hot" (rect 21 107 38 120)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 0 128) + (input) + (text "sound_high_level" (rect 0 0 97 13)(font "Arial" (font_size 8))) + (text "sound_high_level" (rect 21 123 118 136)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)) + ) + (port + (pt 216 32) + (output) + (text "speed[1..0]" (rect 0 0 62 13)(font "Arial" (font_size 8))) + (text "speed[1..0]" (rect 133 27 195 40)(font "Arial" (font_size 8))) + (line (pt 216 32)(pt 200 32)(line_width 3)) + ) + (port + (pt 216 48) + (output) + (text "fan_auto" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "fan_auto" (rect 146 43 195 56)(font "Arial" (font_size 8))) + (line (pt 216 48)(pt 200 48)) + ) + (port + (pt 216 64) + (output) + (text "alarm" (rect 0 0 31 13)(font "Arial" (font_size 8))) + (text "alarm" (rect 164 59 195 72)(font "Arial" (font_size 8))) + (line (pt 216 64)(pt 200 64)) + ) + (drawing + (rectangle (rect 16 16 200 144)) + ) +) diff --git a/FPGA/top/demo_io_pin.tcl b/FPGA/top/demo_io_pin.tcl new file mode 100644 index 0000000..c28dbc8 --- /dev/null +++ b/FPGA/top/demo_io_pin.tcl @@ -0,0 +1,17 @@ +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn + +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_P25 -to speed_user[0] + +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_N25 -to alarm_user + +set_location_assignment PIN_V2 -to hot +set_location_assignment PIN_V1 -to sound_high_level + +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_AB21 -to speed[0] + +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AE23 -to alarm \ No newline at end of file diff --git a/FPGA/top/display.bsf b/FPGA/top/display.bsf new file mode 100644 index 0000000..ed4adb7 --- /dev/null +++ b/FPGA/top/display.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 192 112) + (text "display" (rect 5 0 46 13)(font "Arial" (font_size 8))) + (text "inst" (rect 8 81 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "fan_auto" (rect 0 0 49 13)(font "Arial" (font_size 8))) + (text "fan_auto" (rect 21 27 70 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "alarm_user" (rect 0 0 63 13)(font "Arial" (font_size 8))) + (text "alarm_user" (rect 21 43 84 56)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "speed[1..0]" (rect 0 0 62 13)(font "Arial" (font_size 8))) + (text "speed[1..0]" (rect 21 59 83 72)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "hex7[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex7[6..0]" (rect 100 27 155 40)(font "Arial" (font_size 8))) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (port + (pt 176 48) + (output) + (text "hex6[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex6[6..0]" (rect 100 43 155 56)(font "Arial" (font_size 8))) + (line (pt 176 48)(pt 160 48)(line_width 3)) + ) + (port + (pt 176 64) + (output) + (text "hex4[6..0]" (rect 0 0 55 13)(font "Arial" (font_size 8))) + (text "hex4[6..0]" (rect 100 59 155 72)(font "Arial" (font_size 8))) + (line (pt 176 64)(pt 160 64)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 160 80)) + ) +) diff --git a/FPGA/top/lcd_pin.tcl b/FPGA/top/lcd_pin.tcl new file mode 100644 index 0000000..370a473 --- /dev/null +++ b/FPGA/top/lcd_pin.tcl @@ -0,0 +1,13 @@ +set_location_assignment PIN_K1 -to LCD_RS +set_location_assignment PIN_K4 -to LCD_RW +set_location_assignment PIN_K3 -to LCD_EN +set_location_assignment PIN_K2 -to LCD_BLON +set_location_assignment PIN_L4 -to LCD_ON +set_location_assignment PIN_H3 -to LCD_DATA[7] +set_location_assignment PIN_H4 -to LCD_DATA[6] +set_location_assignment PIN_J3 -to LCD_DATA[5] +set_location_assignment PIN_J4 -to LCD_DATA[4] +set_location_assignment PIN_H2 -to LCD_DATA[3] +set_location_assignment PIN_H1 -to LCD_DATA[2] +set_location_assignment PIN_J2 -to LCD_DATA[1] +set_location_assignment PIN_J1 -to LCD_DATA[0] \ No newline at end of file diff --git a/FPGA/top/real_io_pin.tcl b/FPGA/top/real_io_pin.tcl new file mode 100644 index 0000000..1ece41c --- /dev/null +++ b/FPGA/top/real_io_pin.tcl @@ -0,0 +1,22 @@ +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_AE23 -to alarm +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_M23 -to hot +set_location_assignment PIN_K26 -to fan +set_location_assignment PIN_B4 -to aud_bclk +set_location_assignment PIN_A4 -to aud_dacdat +set_location_assignment PIN_C6 -to aud_daclrck +set_location_assignment PIN_A5 -to aud_xck +set_location_assignment PIN_A6 -to i2c_sclk +set_location_assignment PIN_B6 -to i2c_sdat +set_location_assignment PIN_M20 -to sound_high_level +set_location_assignment PIN_Y18 -to led_fan +set_location_assignment PIN_AE22 -to end_config +set_location_assignment PIN_M25 -to xti_mclk \ No newline at end of file diff --git a/FPGA/top/top.bdf b/FPGA/top/top.bdf new file mode 100644 index 0000000..7fd8d63 --- /dev/null +++ b/FPGA/top/top.bdf @@ -0,0 +1,443 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 48 120 216 136) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 20 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 48 136 216 152) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "resetn" (rect 5 0 36 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 40 152 216 168) + (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) + (text "speed_user[1..0]" (rect 5 0 88 11)(font "Arial" )) + (pt 176 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 176 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 48 168 216 184) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "fan_auto_user" (rect 5 0 77 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 48 184 216 200) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "alarm_user" (rect 5 0 62 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 48 200 216 216) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "hot" (rect 5 0 21 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 32 216 216 232) + (text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6))) + (text "sound_high_level" (rect 5 0 92 11)(font "Arial" )) + (pt 184 8) + (drawing + (line (pt 100 12)(pt 125 12)) + (line (pt 100 4)(pt 125 4)) + (line (pt 129 8)(pt 184 8)) + (line (pt 100 12)(pt 100 4)) + (line (pt 125 4)(pt 129 8)) + (line (pt 125 12)(pt 129 8)) + ) + (text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 648 136 824 152) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "speed[1..0]" (rect 90 0 145 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 648 152 824 168) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "fan_auto" (rect 90 0 133 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 648 168 824 184) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "alarm" (rect 90 0 118 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 648 184 824 200) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hex7[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 648 200 824 216) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hex6[6..0]" (rect 90 0 138 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line 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"Arial" (font_size 8))) + (text "hex4[6..0]" (rect 100 59 155 72)(font "Arial" (font_size 8))) + (line (pt 176 64)(pt 160 64)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 160 80)) + ) +) +(connector + (text "speed[1..0]" (rect 580 136 635 147)(font "Arial" )) + (pt 568 152) + (pt 584 152) + (bus) +) +(connector + (text "speed[1..0]" (rect 304 344 359 355)(font "Arial" )) + (pt 368 360) + (pt 296 360) + (bus) +) +(connector + (text "alarm_user" (rect 304 328 360 339)(font "Arial" )) + (pt 368 344) + (pt 296 344) +) +(connector + (text "fan_auto" (rect 304 312 347 323)(font "Arial" )) + (pt 368 328) + (pt 296 328) +) +(connector + (text "fan_auto" (rect 576 152 619 163)(font "Arial" )) + (pt 568 168) + (pt 584 168) +) +(connector + (text "alarm" (rect 576 168 604 179)(font "Arial" )) + (pt 568 184) + (pt 584 184) +) +(connector + (text "hex7[6..0]" (rect 552 312 600 323)(font "Arial" )) + (pt 544 328) + (pt 560 328) + (bus) +) +(connector + (text "hex6[6..0]" (rect 553 328 601 339)(font "Arial" )) + (pt 544 344) + (pt 560 344) + (bus) +) +(connector + (text "hex4[6..0]" (rect 552 344 600 355)(font "Arial" )) + (pt 544 360) + (pt 560 360) + (bus) +) +(connector + (text "speed_user[1..0]" (rect 272 168 354 179)(font "Arial" )) + (pt 352 184) + (pt 264 184) + (bus) +) +(connector + (text "resetn" (rect 272 152 302 163)(font "Arial" )) + (pt 352 168) + (pt 264 168) +) +(connector + (text "clk" (rect 272 136 286 147)(font "Arial" )) + (pt 352 152) + (pt 264 152) +) +(connector + (text "fan_auto_user" (rect 272 184 343 195)(font "Arial" )) + (pt 352 200) + (pt 264 200) +) +(connector + (text "alarm_user" (rect 272 200 328 211)(font "Arial" )) + (pt 352 216) + (pt 264 216) +) +(connector + (text "hot" (rect 272 216 287 227)(font "Arial" )) + (pt 352 232) + (pt 264 232) +) +(connector + (text "sound_high_level" (rect 272 232 358 243)(font "Arial" )) + (pt 352 248) + (pt 264 248) +) diff --git a/FPGA/top/top.qpf b/FPGA/top/top.qpf new file mode 100644 index 0000000..335bfc5 --- /dev/null +++ b/FPGA/top/top.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:38:55 April 11, 2014 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "22:38:55 April 11, 2014" + +# Revisions + +PROJECT_REVISION = "top" diff --git a/FPGA/top/top.qsf b/FPGA/top/top.qsf new file mode 100644 index 0000000..923b663 --- /dev/null +++ b/FPGA/top/top.qsf @@ -0,0 +1,161 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:38:55 April 11, 2014 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# top_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C35F672C6 +set_global_assignment -name TOP_LEVEL_ENTITY top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:38:55 APRIL 11, 2014" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" +set_location_assignment PIN_AF10 -to hex0[0] +set_location_assignment PIN_AB12 -to hex0[1] +set_location_assignment PIN_AC12 -to hex0[2] +set_location_assignment PIN_AD11 -to hex0[3] +set_location_assignment PIN_AE11 -to hex0[4] +set_location_assignment PIN_V14 -to hex0[5] +set_location_assignment PIN_V13 -to hex0[6] +set_location_assignment PIN_V20 -to hex1[0] +set_location_assignment PIN_V21 -to hex1[1] +set_location_assignment PIN_W21 -to hex1[2] +set_location_assignment PIN_Y22 -to hex1[3] +set_location_assignment PIN_AA24 -to hex1[4] +set_location_assignment PIN_AA23 -to hex1[5] +set_location_assignment PIN_AB24 -to hex1[6] +set_location_assignment PIN_AB23 -to hex2[0] +set_location_assignment PIN_V22 -to hex2[1] +set_location_assignment PIN_AC25 -to hex2[2] +set_location_assignment PIN_AC26 -to hex2[3] +set_location_assignment PIN_AB26 -to hex2[4] +set_location_assignment PIN_AB25 -to hex2[5] +set_location_assignment PIN_Y24 -to hex2[6] +set_location_assignment PIN_Y23 -to hex3[0] +set_location_assignment PIN_AA25 -to hex3[1] +set_location_assignment PIN_AA26 -to hex3[2] +set_location_assignment PIN_Y26 -to hex3[3] +set_location_assignment PIN_Y25 -to hex3[4] +set_location_assignment PIN_U22 -to hex3[5] +set_location_assignment PIN_W24 -to hex3[6] +set_location_assignment PIN_U9 -to hex4[0] +set_location_assignment PIN_U1 -to hex4[1] +set_location_assignment PIN_U2 -to hex4[2] +set_location_assignment PIN_T4 -to hex4[3] +set_location_assignment PIN_R7 -to hex4[4] +set_location_assignment PIN_R6 -to hex4[5] +set_location_assignment PIN_T3 -to hex4[6] +set_location_assignment PIN_T2 -to hex5[0] +set_location_assignment PIN_P6 -to hex5[1] +set_location_assignment PIN_P7 -to hex5[2] +set_location_assignment PIN_T9 -to hex5[3] +set_location_assignment PIN_R5 -to hex5[4] +set_location_assignment PIN_R4 -to hex5[5] +set_location_assignment PIN_R3 -to hex5[6] +set_location_assignment PIN_R2 -to hex6[0] +set_location_assignment PIN_P4 -to hex6[1] +set_location_assignment PIN_P3 -to hex6[2] +set_location_assignment PIN_M2 -to hex6[3] +set_location_assignment PIN_M3 -to hex6[4] +set_location_assignment PIN_M5 -to hex6[5] +set_location_assignment PIN_M4 -to hex6[6] +set_location_assignment PIN_L3 -to hex7[0] +set_location_assignment PIN_L2 -to hex7[1] +set_location_assignment PIN_L9 -to hex7[2] +set_location_assignment PIN_L6 -to hex7[3] +set_location_assignment PIN_L7 -to hex7[4] +set_location_assignment PIN_P9 -to hex7[5] +set_location_assignment PIN_N9 -to hex7[6] +set_location_assignment PIN_K1 -to LCD_RS +set_location_assignment PIN_K4 -to LCD_RW +set_location_assignment PIN_K3 -to LCD_EN +set_location_assignment PIN_K2 -to LCD_BLON +set_location_assignment PIN_L4 -to LCD_ON +set_location_assignment PIN_H3 -to LCD_DATA[7] +set_location_assignment PIN_H4 -to LCD_DATA[6] +set_location_assignment PIN_J3 -to LCD_DATA[5] +set_location_assignment PIN_J4 -to LCD_DATA[4] +set_location_assignment PIN_H2 -to LCD_DATA[3] +set_location_assignment PIN_H1 -to LCD_DATA[2] +set_location_assignment PIN_J2 -to LCD_DATA[1] +set_location_assignment PIN_J1 -to LCD_DATA[0] +set_location_assignment PIN_N2 -to clk +set_location_assignment PIN_G26 -to resetn +set_location_assignment PIN_AE14 -to speed_user[1] +set_location_assignment PIN_P25 -to speed_user[0] +set_location_assignment PIN_N26 -to fan_auto_user +set_location_assignment PIN_N25 -to alarm_user +set_location_assignment PIN_V2 -to hot +set_location_assignment PIN_V1 -to sound_high_level +set_location_assignment PIN_AC22 -to speed[1] +set_location_assignment PIN_AB21 -to speed[0] +set_location_assignment PIN_AF23 -to fan_auto +set_location_assignment PIN_AE23 -to alarm +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE ../vhdl/seven_segment_decoder.vhd +set_global_assignment -name VHDL_FILE ../vhdl/rom_sinus.vhd +set_global_assignment -name VHDL_FILE ../vhdl/message.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd_message.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd_controller.vhd +set_global_assignment -name VHDL_FILE ../vhdl/lcd.vhd +set_global_assignment -name VHDL_FILE ../vhdl/i2c_master.vhd +set_global_assignment -name VHDL_FILE ../vhdl/dds_sinus.vhd +set_global_assignment -name VHDL_FILE ../vhdl/codec_dac.vhd +set_global_assignment -name VHDL_FILE ../vhdl/codec_config.vhd +set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd +set_global_assignment -name VHDL_FILE ../display/lpm_constant_f.vhd +set_global_assignment -name SOURCE_FILE ../display/lpm_constant_f.cmp +set_global_assignment -name VHDL_FILE ../display/lpm_constant_a.vhd +set_global_assignment -name SOURCE_FILE ../display/lpm_constant_a.cmp +set_global_assignment -name VHDL_FILE ../display/lpm_constant_1.vhd +set_global_assignment -name SOURCE_FILE ../display/lpm_constant_1.cmp +set_global_assignment -name BDF_FILE ../commande/fan.bdf +set_global_assignment -name BDF_FILE ../commande/alarm.bdf +set_global_assignment -name BDF_FILE ../display/display.bdf +set_global_assignment -name BDF_FILE ../commande/commande.bdf +set_global_assignment -name BDF_FILE top.bdf +set_global_assignment -name TCL_SCRIPT_FILE 7seg_pin.tcl +set_global_assignment -name TCL_SCRIPT_FILE lcd_pin.tcl +set_global_assignment -name TCL_SCRIPT_FILE real_io_pin.tcl +set_global_assignment -name TCL_SCRIPT_FILE demo_io_pin.tcl +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- cgit v1.2.3