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--      Clock Divider
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-- Creation : A. Exertier, 2005
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library ieee;
use ieee.std_logic_1164.all;

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--                PARAMETRES GENERIQUES
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-- board_frequency  : frequency of the FPGA
-- user_frequency   : desired frequency
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--                   INPUTS
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-- clk      : main clock
-- resetn   : asynchronous active low reset
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--                   OUTPUT
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-- en_user  : signal at user_frequency
--            set to 1 only 1 main clock cycle
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entity clock_divider is	
  generic(
     board_frequency   : real :=50_000_000.0; -- 50 MHz
	 user_frequency    : real :=4.0);          -- 4 Hz
  Port (
    clk           : in  std_logic;  
    resetn        : in  std_logic;  -- active low
	en_user       : out std_logic);
end clock_divider;

architecture RTL of clock_divider is
  constant max     : natural := integer(board_frequency/user_frequency);  
begin
  process(clk,resetn)
      variable counter : natural range 0 to max-1;
  begin
   if resetn='0' then 			 
     counter := 0;
     en_user <= '0';
   elsif rising_edge(clk) then 
     if counter = max-1 then 
       counter	:= 0;
       en_user <= '1';	
     else 
       counter := counter+1;
       en_user <= '0';
     end if;
   end if;
  end process;
end RTL;