summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPacien TRAN-GIRARD2014-06-13 16:06:19 +0200
committerPacien TRAN-GIRARD2014-06-13 16:06:19 +0200
commit70318492f3472ff2ec3b1735cf69a4eef1f6a51d (patch)
tree0f4243099ea9379bc164dc37a9fee3ab255f0f7e
parentd091bb2cb82f66d187df8f3aba6afcf4041b72ce (diff)
downloadfpga-home-automation-70318492f3472ff2ec3b1735cf69a4eef1f6a51d.tar.gz
Update project
Diffstat
-rw-r--r--.gitignore16
-rw-r--r--.project6
-rw-r--r--.texlipse14
-rw-r--r--FPGA/LCD_message/LCD_controller.bsf141
-rw-r--r--FPGA/LCD_message/LCD_message.qpf30
-rw-r--r--FPGA/LCD_message/LCD_message.qsf157
-rw-r--r--FPGA/LCD_message/LCD_message.qwsbin0 -> 1442 bytes
-rw-r--r--FPGA/LCD_message/lcd.bsf154
-rw-r--r--FPGA/LCD_message/lcd_message.bsf85
-rw-r--r--FPGA/LCD_message/message.bsf43
-rw-r--r--FPGA/bind_all.tcl91
-rw-r--r--FPGA/codec_clock/clock_divider.bsf61
-rw-r--r--FPGA/codec_clock/codec_clock.bdf112
-rw-r--r--FPGA/codec_clock/codec_clock.bsf50
-rw-r--r--FPGA/codec_clock/codec_clock.qpf30
-rw-r--r--FPGA/codec_clock/codec_clock.qsf78
-rw-r--r--FPGA/codec_clock/codec_clock.qwsbin0 -> 2276 bytes
-rw-r--r--FPGA/commande/commande_pin.tcl.bak17
-rw-r--r--FPGA/display/clock_divider.bsf61
-rw-r--r--FPGA/display/display.bdf369
-rw-r--r--FPGA/display/display.bsf83
-rw-r--r--FPGA/display/display.qsf7
-rw-r--r--FPGA/display/display.qwsbin1438 -> 1438 bytes
-rw-r--r--FPGA/display/greybox_tmp/cbx_args.txt7
-rw-r--r--FPGA/display/lpm_constant7nada.bsf49
-rw-r--r--FPGA/display/lpm_constant7nada.cmp21
-rw-r--r--FPGA/display/lpm_constant7nada.qip5
-rw-r--r--FPGA/display/lpm_constant7nada.vhd109
-rw-r--r--FPGA/display/lpm_constant_a.bsf10
-rw-r--r--FPGA/display/lpm_constant_a.qip5
-rw-r--r--FPGA/display/lpm_constant_a.vhd2
-rw-r--r--FPGA/display/lpm_constant_f.qip0
-rw-r--r--FPGA/display/lpm_counter0.qip0
-rw-r--r--FPGA/display/lpm_shiftreg0.bsf86
-rw-r--r--FPGA/display/lpm_shiftreg0.cmp26
-rw-r--r--FPGA/display/lpm_shiftreg0.qip5
-rw-r--r--FPGA/display/lpm_shiftreg0.vhd146
-rw-r--r--FPGA/display/useless.bdf968
-rw-r--r--FPGA/display/useless.bsf71
-rw-r--r--FPGA/pwm.tcl6
-rw-r--r--FPGA/pwm/greybox_tmp/cbx_args.txt7
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v52
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v51
-rw-r--r--FPGA/pwm/lpm_compare0.bsf62
-rw-r--r--FPGA/pwm/lpm_compare0.cmp23
-rw-r--r--FPGA/pwm/lpm_compare0.qip5
-rw-r--r--FPGA/pwm/lpm_compare0.vhd126
-rw-r--r--FPGA/pwm/lpm_constant0.bsf49
-rw-r--r--FPGA/pwm/lpm_constant0.cmp21
-rw-r--r--FPGA/pwm/lpm_constant0.qip5
-rw-r--r--FPGA/pwm/lpm_constant0.vhd109
-rw-r--r--FPGA/pwm/lpm_constant1.bsf49
-rw-r--r--FPGA/pwm/lpm_constant1.cmp21
-rw-r--r--FPGA/pwm/lpm_constant1.qip5
-rw-r--r--FPGA/pwm/lpm_constant1.vhd109
-rw-r--r--FPGA/pwm/lpm_constant2.bsf49
-rw-r--r--FPGA/pwm/lpm_constant2.cmp21
-rw-r--r--FPGA/pwm/lpm_constant2.qip5
-rw-r--r--FPGA/pwm/lpm_constant2.vhd109
-rw-r--r--FPGA/pwm/lpm_constant3.bsf49
-rw-r--r--FPGA/pwm/lpm_constant3.cmp21
-rw-r--r--FPGA/pwm/lpm_constant3.qip5
-rw-r--r--FPGA/pwm/lpm_constant3.vhd109
-rw-r--r--FPGA/pwm/lpm_counter0.bsf64
-rw-r--r--FPGA/pwm/lpm_counter0.cmp23
-rw-r--r--FPGA/pwm/lpm_counter0.qip5
-rw-r--r--FPGA/pwm/lpm_counter0.vhd130
-rw-r--r--FPGA/pwm/lpm_counter1.bsf65
-rw-r--r--FPGA/pwm/lpm_counter1.cmp23
-rw-r--r--FPGA/pwm/lpm_counter1.qip5
-rw-r--r--FPGA/pwm/lpm_counter1.vhd133
-rw-r--r--FPGA/pwm/lpm_mux0.bsf82
-rw-r--r--FPGA/pwm/lpm_mux0.cmp26
-rw-r--r--FPGA/pwm/lpm_mux0.qip5
-rw-r--r--FPGA/pwm/lpm_mux0.vhd210
-rw-r--r--FPGA/pwm/pwm.bdf502
-rw-r--r--FPGA/pwm/pwm.bsf64
-rw-r--r--FPGA/pwm/pwm.qpf30
-rw-r--r--FPGA/pwm/pwm.qsf71
-rw-r--r--FPGA/pwm/pwm.qwsbin0 -> 1406 bytes
-rw-r--r--FPGA/pwm/pwm.tcl6
-rw-r--r--FPGA/sound_gene/clock_divider.bsf61
-rw-r--r--FPGA/sound_gene/codec_clock.bsf50
-rw-r--r--FPGA/sound_gene/codec_config.bsf75
-rw-r--r--FPGA/sound_gene/codec_dac.bsf113
-rw-r--r--FPGA/sound_gene/dds_sinus.bsf68
-rw-r--r--FPGA/sound_gene/sound_gene.bdf927
-rw-r--r--FPGA/sound_gene/sound_gene.bsf113
-rw-r--r--FPGA/sound_gene/sound_gene.qpf30
-rw-r--r--FPGA/sound_gene/sound_gene.qsf85
-rw-r--r--FPGA/sound_gene/sound_gene.qwsbin0 -> 897 bytes
-rw-r--r--FPGA/top/LCD_controller.bsf141
-rw-r--r--FPGA/top/clock_divider.bsf61
-rw-r--r--FPGA/top/codec_clock.bsf50
-rw-r--r--FPGA/top/codec_clock.qsf78
-rw-r--r--FPGA/top/codec_config.bsf75
-rw-r--r--FPGA/top/codec_dac.bsf113
-rw-r--r--FPGA/top/dds_sinus.bsf68
-rw-r--r--FPGA/top/display.bsf83
-rw-r--r--FPGA/top/greybox_tmp/cbx_args.txt9
-rw-r--r--FPGA/top/lcd_message.bsf85
-rw-r--r--FPGA/top/lpm_compare0.bsf62
-rw-r--r--FPGA/top/lpm_counter0.bsf64
-rw-r--r--FPGA/top/lpm_counter1.bsf65
-rw-r--r--FPGA/top/lpm_counter1.qip0
-rw-r--r--FPGA/top/lpm_mux0.bsf82
-rw-r--r--FPGA/top/message.bsf43
-rw-r--r--FPGA/top/pwm.bsf64
-rw-r--r--FPGA/top/sound_gene.bsf113
-rw-r--r--FPGA/top/top.bdf1015
-rw-r--r--FPGA/top/top.bsf232
-rw-r--r--FPGA/top/top.qsf57
-rw-r--r--FPGA/top/top.tcl212
-rw-r--r--FPGA/top/useless.bsf71
-rw-r--r--FPGA/vhdl/LCD_message.bdf415
-rw-r--r--FPGA/vhdl/codec_config.vhd21
-rw-r--r--FPGA/vhdl/dds_sinus.vhd4
-rw-r--r--FPGA/vhdl/greybox_tmp/cbx_args.txt12
-rw-r--r--FPGA/vhdl/i2c_master.vhd526
-rw-r--r--FPGA/vhdl/lpm_shiftreg0.qip0
-rw-r--r--FPGA/vhdl/message.vhd66
-rw-r--r--FPGA/vhdl/message.vhd.bak67
122 files changed, 10569 insertions, 534 deletions
diff --git a/.gitignore b/.gitignore
index 1e59957..bad0c8c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,21 @@
1# Directories #
2/build/
3/bin/
4target/
5
6# OS Files #
7.DS_Store
8
9*.class
1 10
2# Quartus II output files 11# Quartus II output files
3output_files/ 12output_files/
4db/ 13db/
5incremental_db/ 14incremental_db/
15
16######################
17# TeXlipse
18######################
19
20report/out/**
21report/tmp/**
diff --git a/.project b/.project
index 40bb52c..308973b 100644
--- a/.project
+++ b/.project
@@ -5,7 +5,13 @@
5 <projects> 5 <projects>
6 </projects> 6 </projects>
7 <buildSpec> 7 <buildSpec>
8 <buildCommand>
9 <name>net.sourceforge.texlipse.builder.TexlipseBuilder</name>
10 <arguments>
11 </arguments>
12 </buildCommand>
8 </buildSpec> 13 </buildSpec>
9 <natures>