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Diffstat (limited to 'FPGA/pwm/lpm_counter0.cmp')
-rw-r--r-- | FPGA/pwm/lpm_counter0.cmp | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/FPGA/pwm/lpm_counter0.cmp b/FPGA/pwm/lpm_counter0.cmp deleted file mode 100644 index f505116..0000000 --- a/FPGA/pwm/lpm_counter0.cmp +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | --Copyright (C) 1991-2013 Altera Corporation | ||
2 | --Your use of Altera Corporation's design tools, logic functions | ||
3 | --and other software and tools, and its AMPP partner logic | ||
4 | --functions, and any output files from any of the foregoing | ||
5 | --(including device programming or simulation files), and any | ||
6 | --associated documentation or information are expressly subject | ||
7 | --to the terms and conditions of the Altera Program License | ||
8 | --Subscription Agreement, Altera MegaCore Function License | ||
9 | --Agreement, or other applicable license agreement, including, | ||
10 | --without limitation, that your use is for the sole purpose of | ||
11 | --programming logic devices manufactured by Altera and sold by | ||
12 | --Altera or its authorized distributors. Please refer to the | ||
13 | --applicable agreement for further details. | ||
14 | |||
15 | |||
16 | component lpm_counter0 | ||
17 | PORT | ||
18 | ( | ||
19 | aclr : IN STD_LOGIC ; | ||
20 | clock : IN STD_LOGIC ; | ||
21 | q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0) | ||
22 | ); | ||
23 | end component; | ||