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1--Copyright (C) 1991-2013 Altera Corporation
2--Your use of Altera Corporation's design tools, logic functions
3--and other software and tools, and its AMPP partner logic
4--functions, and any output files from any of the foregoing
5--(including device programming or simulation files), and any
6--associated documentation or information are expressly subject
7--to the terms and conditions of the Altera Program License
8--Subscription Agreement, Altera MegaCore Function License
9--Agreement, or other applicable license agreement, including,
10--without limitation, that your use is for the sole purpose of
11--programming logic devices manufactured by Altera and sold by
12--Altera or its authorized distributors. Please refer to the
13--applicable agreement for further details.
14
15
16component lpm_mux0
17 PORT
18 (
19 data0x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
20 data1x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
21 data2x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
22 data3x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
23 sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
24 result : OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
25 );
26end component;