summaryrefslogtreecommitdiff
path: root/FPGA/pwm/lpm_mux0.vhd
diff options
context:
space:
mode:
Diffstat (limited to 'FPGA/pwm/lpm_mux0.vhd')
-rw-r--r--FPGA/pwm/lpm_mux0.vhd210
1 files changed, 210 insertions, 0 deletions
diff --git a/FPGA/pwm/lpm_mux0.vhd b/FPGA/pwm/lpm_mux0.vhd
new file mode 100644
index 0000000..7d2f511
--- /dev/null
+++ b/FPGA/pwm/lpm_mux0.vhd
@@ -0,0 +1,210 @@
1-- megafunction wizard: %LPM_MUX%
2-- GENERATION: STANDARD
3-- VERSION: WM1.0
4-- MODULE: LPM_MUX
5
6-- ============================================================
7-- File Name: lpm_mux0.vhd
8-- Megafunction Name(s):
9-- LPM_MUX
10--
11-- Simulation Library Files(s):
12-- lpm
13-- ============================================================
14-- ************************************************************
15-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16--
17-- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
18-- ************************************************************
19
20
21--Copyright (C) 1991-2013 Altera Corporation
22--Your use of Altera Corporation's design tools, logic functions
23--and other software and tools, and its AMPP partner logic
24--functions, and any output files from any of the foregoing
25--(including device programming or simulation files), and any
26--associated documentation or information are expressly subject
27--to the terms and conditions of the Altera Program License
28--Subscription Agreement, Altera MegaCore Function License
29--Agreement, or other applicable license agreement, including,
30--without limitation, that your use is for the sole purpose of
31--programming logic devices manufactured by Altera and sold by
32--Altera or its authorized distributors. Please refer to the
33--applicable agreement for further details.
34
35
36LIBRARY ieee;
37USE ieee.std_logic_1164.all;
38
39LIBRARY lpm;
40USE lpm.lpm_components.all;
41
42ENTITY lpm_mux0 IS
43 PORT
44 (
45 data0x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
46 data1x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
47 data2x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
48 data3x : IN STD_LOGIC_VECTOR (22 DOWNTO 0);
49 sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
50 result : OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
51 );
52END lpm_mux0;
53
54
55ARCHITECTURE SYN OF lpm_mux0 IS
56
57-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
58
59 SIGNAL sub_wire0 : STD_LOGIC_VECTOR (22 DOWNTO 0);
60 SIGNAL sub_wire1 : STD_LOGIC_VECTOR (22 DOWNTO 0);
61 SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 22 DOWNTO 0);
62 SIGNAL sub_wire3 : STD_LOGIC_VECTOR (22 DOWNTO 0);
63 SIGNAL sub_wire4 : STD_LOGIC_VECTOR (22 DOWNTO 0);
64 SIGNAL sub_wire5 : STD_LOGIC_VECTOR (22 DOWNTO 0);
65
66BEGIN
67 sub_wire5 <= data0x(22 DOWNTO 0);
68 sub_wire4 <= data1x(22 DOWNTO 0);
69 sub_wire3 <= data2x(22 DOWNTO 0);
70 result <= sub_wire0(22 DOWNTO 0);
71 sub_wire1 <= data3x(22 DOWNTO 0);
72 sub_wire2(3, 0) <= sub_wire1(0);
73 sub_wire2(3, 1) <= sub_wire1(1);
74 sub_wire2(3, 2) <= sub_wire1(2);
75 sub_wire2(3, 3) <= sub_wire1(3);
76 sub_wire2(3, 4) <= sub_wire1(4);
77 sub_wire2(3, 5) <= sub_wire1(5);
78 sub_wire2(3, 6) <= sub_wire1(6);
79 sub_wire2(3, 7) <= sub_wire1(7);
80 sub_wire2(3, 8) <= sub_wire1(8);
81 sub_wire2(3, 9) <= sub_wire1(9);
82 sub_wire2(3, 10) <= sub_wire1(10);
83 sub_wire2(3, 11) <= sub_wire1(11);
84 sub_wire2(3, 12) <= sub_wire1(12);
85 sub_wire2(3, 13) <= sub_wire1(13);
86 sub_wire2(3, 14) <= sub_wire1(14);
87 sub_wire2(3, 15) <= sub_wire1(15);
88 sub_wire2(3, 16) <= sub_wire1(16);
89 sub_wire2(3, 17) <= sub_wire1(17);
90 sub_wire2(3, 18) <= sub_wire1(18);
91 sub_wire2(3, 19) <= sub_wire1(19);
92 sub_wire2(3, 20) <= sub_wire1(20);
93 sub_wire2(3, 21) <= sub_wire1(21);
94 sub_wire2(3, 22) <= sub_wire1(22);
95 sub_wire2(2, 0) <= sub_wire3(0);
96 sub_wire2(2, 1) <= sub_wire3(1);
97 sub_wire2(2, 2) <= sub_wire3(2);
98 sub_wire2(2, 3) <= sub_wire3(3);
99 sub_wire2(2, 4) <= sub_wire3(4);
100 sub_wire2(2, 5) <= sub_wire3(5);
101 sub_wire2(2, 6) <= sub_wire3(6);
102 sub_wire2(2, 7) <= sub_wire3(7);
103 sub_wire2(2, 8) <= sub_wire3(8);
104 sub_wire2(2, 9) <= sub_wire3(9);
105 sub_wire2(2, 10) <= sub_wire3(10);
106 sub_wire2(2, 11) <= sub_wire3(11);
107 sub_wire2(2, 12) <= sub_wire3(12);
108 sub_wire2(2, 13) <= sub_wire3(13);
109 sub_wire2(2, 14) <= sub_wire3(14);
110 sub_wire2(2, 15) <= sub_wire3(15);
111 sub_wire2(2, 16) <= sub_wire3(16);
112 sub_wire2(2, 17) <= sub_wire3(17);
113 sub_wire2(2, 18) <= sub_wire3(18);
114 sub_wire2(2, 19) <= sub_wire3(19);
115 sub_wire2(2, 20) <= sub_wire3(20);
116 sub_wire2(2, 21) <= sub_wire3(21);
117 sub_wire2(2, 22) <= sub_wire3(22);
118 sub_wire2(1, 0) <= sub_wire4(0);
119 sub_wire2(1, 1) <= sub_wire4(1);
120 sub_wire2(1, 2) <= sub_wire4(2);
121 sub_wire2(1, 3) <= sub_wire4(3);
122 sub_wire2(1, 4) <= sub_wire4(4);
123 sub_wire2(1, 5) <= sub_wire4(5);
124 sub_wire2(1, 6) <= sub_wire4(6);
125 sub_wire2(1, 7) <= sub_wire4(7);
126 sub_wire2(1, 8) <= sub_wire4(8);
127 sub_wire2(1, 9) <= sub_wire4(9);
128 sub_wire2(1, 10) <= sub_wire4(10);
129 sub_wire2(1, 11) <= sub_wire4(11);
130 sub_wire2(1, 12) <= sub_wire4(12);
131 sub_wire2(1, 13) <= sub_wire4(13);
132 sub_wire2(1, 14) <= sub_wire4(14);
133 sub_wire2(1, 15) <= sub_wire4(15);
134 sub_wire2(1, 16) <= sub_wire4(16);
135 sub_wire2(1, 17) <= sub_wire4(17);
136 sub_wire2(1, 18) <= sub_wire4(18);
137 sub_wire2(1, 19) <= sub_wire4(19);
138 sub_wire2(1, 20) <= sub_wire4(20);
139 sub_wire2(1, 21) <= sub_wire4(21);
140 sub_wire2(1, 22) <= sub_wire4(22);
141 sub_wire2(0, 0) <= sub_wire5(0);
142 sub_wire2(0, 1) <= sub_wire5(1);
143 sub_wire2(0, 2) <= sub_wire5(2);
144 sub_wire2(0, 3) <= sub_wire5(3);
145 sub_wire2(0, 4) <= sub_wire5(4);
146 sub_wire2(0, 5) <= sub_wire5(5);
147 sub_wire2(0, 6) <= sub_wire5(6);
148 sub_wire2(0, 7) <= sub_wire5(7);
149 sub_wire2(0, 8) <= sub_wire5(8);
150 sub_wire2(0, 9) <= sub_wire5(9);
151 sub_wire2(0, 10) <= sub_wire5(10);
152 sub_wire2(0, 11) <= sub_wire5(11);
153 sub_wire2(0, 12) <= sub_wire5(12);
154 sub_wire2(0, 13) <= sub_wire5(13);
155 sub_wire2(0, 14) <= sub_wire5(14);
156 sub_wire2(0, 15) <= sub_wire5(15);
157 sub_wire2(0, 16) <= sub_wire5(16);
158 sub_wire2(0, 17) <= sub_wire5(17);
159 sub_wire2(0, 18) <= sub_wire5(18);
160 sub_wire2(0, 19) <= sub_wire5(19);
161 sub_wire2(0, 20) <= sub_wire5(20);
162 sub_wire2(0, 21) <= sub_wire5(21);
163 sub_wire2(0, 22) <= sub_wire5(22);
164
165 LPM_MUX_component : LPM_MUX
166 GENERIC MAP (
167 lpm_size => 4,
168 lpm_type => "LPM_MUX",
169 lpm_width => 23,
170 lpm_widths => 2
171 )
172 PORT MAP (
173 data => sub_wire2,
174 sel => sel,
175 result => sub_wire0
176 );
177
178
179
180END SYN;
181
182-- ============================================================
183-- CNX file retrieval info
184-- ============================================================
185-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
186-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
187-- Retrieval info: PRIVATE: new_diagram STRING "1"
188-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
189-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
190-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
191-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "23"
192-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
193-- Retrieval info: USED_PORT: data0x 0 0 23 0 INPUT NODEFVAL "data0x[22..0]"
194-- Retrieval info: USED_PORT: data1x 0 0 23 0 INPUT NODEFVAL "data1x[22..0]"
195-- Retrieval info: USED_PORT: data2x 0 0 23 0 INPUT NODEFVAL "data2x[22..0]"
196-- Retrieval info: USED_PORT: data3x 0 0 23 0 INPUT NODEFVAL "data3x[22..0]"
197-- Retrieval info: USED_PORT: result 0 0 23 0 OUTPUT NODEFVAL "result[22..0]"
198-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
199-- Retrieval info: CONNECT: @data 1 0 23 0 data0x 0 0 23 0
200-- Retrieval info: CONNECT: @data 1 1 23 0 data1x 0 0 23 0
201-- Retrieval info: CONNECT: @data 1 2 23 0 data2x 0 0 23 0
202-- Retrieval info: CONNECT: @data 1 3 23 0 data3x 0 0 23 0
203-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
204-- Retrieval info: CONNECT: result 0 0 23 0 @result 0 0 23 0
205-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
206-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE
207-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
208-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE
209-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
210-- Retrieval info: LIB_FILE: lpm
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 06:10:48 +0000