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authorValerio Virgillito2012-03-06 16:17:54 -0800
committerValerio Virgillito2012-03-06 16:17:54 -0800
commitc2805e03c84b6e598556fd06d1ede7aaeea7ce9c (patch)
treeb033421762f5e0fedbc8700bfc1f175c7c5cabcf /imports/codemirror/mode/verilog/index.html
parent1cd89d4d06e3a8f2c221628b19cf26a2c69f5d3f (diff)
downloadninja-c2805e03c84b6e598556fd06d1ede7aaeea7ce9c.tar.gz
Squashed commit FileIO-Build-Candidate into Master
Fixing issues with HTML and CSS URLs. Adjusted RegEx logic. Also code a mirror update and undo/redo changes were merged into this request. Signed-off-by: Valerio Virgillito <valerio@motorola.com>
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1<!doctype html>
2<html>
3 <head>
4 <title>CodeMirror: Verilog mode</title>
5 <link rel="stylesheet" href="../../lib/codemirror.css">
6 <script src="../../lib/codemirror.js"></script>
7 <script src="verilog.js"></script>
8 <link rel="stylesheet" href="../../doc/docs.css">
9 <style>.CodeMirror {border: 2px inset #dee;}</style>
10 </head>
11 <body>
12 <h1>CodeMirror: Verilog mode</h1>
13
14<form><textarea id="code" name="code">
15/* Verilog demo code */
16
17//////////////////////////////////////////////////////////////////////
18//// ////
19//// wb_master_model.v ////
20//// ////
21//// This file is part of the SPI IP core project ////
22//// http://www.opencores.org/projects/spi/ ////
23//// ////
24//// Author(s): ////
25//// - Simon Srot (simons@opencores.org) ////
26//// ////
27//// Based on: ////
28//// - i2c/bench/verilog/wb_master_model.v ////
29//// Copyright (C) 2001 Richard Herveille ////
30//// ////
31//// All additional information is avaliable in the Readme.txt ////
32//// file. ////
33//// ////
34//////////////////////////////////////////////////////////////////////
35//// ////
36//// Copyright (C) 2002 Authors ////
37//// ////
38//// This source file may be used and distributed without ////
39//// restriction provided that this copyright statement is not ////
40//// removed from the file and that any derivative work contains ////
41//// the original copyright notice and the associated disclaimer. ////
42//// ////
43//// This source file is free software; you can redistribute it ////
44//// and/or modify it under the terms of the GNU Lesser General ////
45//// Public License as published by the Free Software Foundation; ////
46//// either version 2.1 of the License, or (at your option) any ////
47//// later version. ////
48//// ////
49//// This source is distributed in the hope that it will be ////
50//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
51//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
52//// PURPOSE. See the GNU Lesser General Public License for more ////
53//// details. ////
54//// ////
55//// You should have received a copy of the GNU Lesser General ////
56//// Public License along with this source; if not, download it ////
57//// from http://www.opencores.org/lgpl.shtml ////
58//// ////
59//////////////////////////////////////////////////////////////////////
60
61`include "timescale.v"
62
63module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
64
65 parameter dwidth = 32;
66 parameter awidth = 32;
67
68 input clk, rst;
69 output [awidth -1:0] adr;
70 input [dwidth -1:0] din;
71 output [dwidth -1:0] dout;
72 output cyc, stb;
73 output we;
74 output [dwidth/8 -1:0] sel;
75 input ack, err, rty;
76
77 // Internal signals
78 reg [awidth -1:0] adr;
79 reg [dwidth -1:0] dout;
80 reg cyc, stb;
81 reg we;
82 reg [dwidth/8 -1:0] sel;
83
84 reg [dwidth -1:0] q;
85
86 // Memory Logic
87 initial
88 begin
89 adr = {awidth{1'bx}};
90 dout = {dwidth{1'bx}};
91 cyc = 1'b0;
92 stb = 1'bx;
93 we = 1'hx;
94 sel = {dwidth/8{1'bx}};
95 #1;
96 end
97
98 // Wishbone write cycle
99 task wb_write;
100 input delay;
101 integer delay;
102
103 input [awidth -1:0] a;
104 input [dwidth -1:0] d;
105
106 begin
107
108 // wait initial delay
109 repeat(delay) @(posedge clk);
110
111 // assert wishbone signal
112 #1;
113 adr = a;
114 dout = d;
115 cyc = 1'b1;
116 stb = 1'b1;
117 we = 1'b1;
118 sel = {dwidth/8{1'b1}};
119 @(posedge clk);
120
121 // wait for acknowledge from slave
122 while(~ack) @(posedge clk);
123
124 // negate wishbone signals
125 #1;
126 cyc = 1'b0;
127 stb = 1'bx;
128 adr = {awidth{1'bx}};
129 dout = {dwidth{1'bx}};
130 we = 1'hx;
131 sel = {dwidth/8{1'bx}};
132
133 end
134 endtask
135
136 // Wishbone read cycle
137 task wb_read;
138 input delay;
139 integer delay;
140
141 input [awidth -1:0] a;
142 output [dwidth -1:0] d;
143
144 begin
145
146 // wait initial delay
147 repeat(delay) @(posedge clk);
148
149 // assert wishbone signals
150 #1;
151 adr = a;
152 dout = {dwidth{1'bx}};
153 cyc = 1'b1;
154 stb = 1'b1;
155 we = 1'b0;
156 sel = {dwidth/8{1'b1}};
157 @(posedge clk);
158
159 // wait for acknowledge from slave
160 while(~ack) @(posedge clk);
161
162 // negate wishbone signals
163 #1;
164 cyc = 1'b0;
165 stb = 1'bx;
166 adr = {awidth{1'bx}};
167 dout = {dwidth{1'bx}};
168 we = 1'hx;
169 sel = {dwidth/8{1'bx}};
170 d = din;
171
172 end
173 endtask
174
175 // Wishbone compare cycle (read data from location and compare with expected data)
176 task wb_cmp;
177 input delay;
178 integer delay;
179
180 input [awidth -1:0] a;
181 input [dwidth -1:0] d_exp;
182
183 begin
184 wb_read (delay, a, q);
185
186 if (d_exp !== q) begin
187 $display("\n--- ERROR: At address 0x%0x, got 0x%0x, expected 0x%0x at time %t", a, q, d_exp, $time);
188 $stop;
189 end
190 end
191 endtask
192
193endmodule
194</textarea></form>
195
196 <script>
197 var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
198 lineNumbers: true,
199 matchBrackets: true,
200 mode: "text/x-verilog"
201 });
202 </script>
203
204 <p>Simple mode that tries to handle Verilog-like languages as well as it
205 can. Takes one configuration parameters: <code>keywords</code>, an
206 object whose property names are the keywords in the language.</p>
207
208 <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
209 </body>
210</html>
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