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authorPacien TRAN-GIRARD2014-06-15 15:28:10 +0200
committerPacien TRAN-GIRARD2014-06-15 15:28:10 +0200
commit4762ef9b7238f67d065775b752ebf51289c1f437 (patch)
treefb88da863e1bbc068d8258b285663013233ebe7b
parentfdd5c7e084529b2a09bed21aef44eb56e82075dc (diff)
downloadfpga-home-automation-4762ef9b7238f67d065775b752ebf51289c1f437.tar.gz
Clean project
Diffstat
-rw-r--r--FPGA/LCD_message/LCD_controller.bsf141
-rw-r--r--FPGA/LCD_message/LCD_message.qpf30
-rw-r--r--FPGA/LCD_message/LCD_message.qsf157
-rw-r--r--FPGA/LCD_message/LCD_message.qwsbin1442 -> 0 bytes
-rw-r--r--FPGA/LCD_message/lcd.bsf154
-rw-r--r--FPGA/LCD_message/lcd_message.bsf85
-rw-r--r--FPGA/LCD_message/message.bsf43
-rw-r--r--FPGA/codec_clock/clock_divider.bsf61
-rw-r--r--FPGA/codec_clock/codec_clock.bdf125
-rw-r--r--FPGA/codec_clock/codec_clock.bsf31
-rw-r--r--FPGA/codec_clock/codec_clock.qsf1
-rw-r--r--FPGA/codec_clock/codec_clock.qwsbin2276 -> 905 bytes
-rw-r--r--FPGA/codec_clock/codec_clock.tcl91
-rw-r--r--FPGA/commande/commande.bdf16
-rw-r--r--FPGA/commande/commande.qwsbin1694 -> 1415 bytes
-rw-r--r--FPGA/commande/commande.tcl84
-rw-r--r--FPGA/display/display.bdf233
-rw-r--r--FPGA/display/display.qsf7
-rw-r--r--FPGA/display/display.qwsbin1438 -> 842 bytes
-rw-r--r--FPGA/display/display.srf1
-rw-r--r--FPGA/display/display.tcl136
-rw-r--r--FPGA/display/greybox_tmp/cbx_args.txt7
-rw-r--r--FPGA/display/lpm_constant_1.qip (renamed from FPGA/pwm/lpm_counter0.qip)8
-rw-r--r--FPGA/display/lpm_constant_1.vhd2
-rw-r--r--FPGA/display/lpm_constant_f.qip5
-rw-r--r--FPGA/display/lpm_counter0.qip0
-rw-r--r--FPGA/pwm/greybox_tmp/cbx_args.txt7
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v52
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v51
-rw-r--r--FPGA/pwm/lpm_counter0.bsf64
-rw-r--r--FPGA/pwm/lpm_counter0.cmp23
-rw-r--r--FPGA/pwm/lpm_counter0.vhd130
-rw-r--r--FPGA/pwm/pwm.qsf1
-rw-r--r--FPGA/pwm/pwm.qwsbin1406 -> 2168 bytes
-rw-r--r--FPGA/pwm/pwm.tcl88
-rw-r--r--FPGA/sound_gene/codec_clock.bsf50
-rw-r--r--FPGA/sound_gene/codec_config.bsf75
-rw-r--r--FPGA/sound_gene/codec_dac.bsf113
-rw-r--r--FPGA/sound_gene/dds_sinus.bsf68
-rw-r--r--FPGA/sound_gene/sound_gene.bdf597
-rw-r--r--FPGA/sound_gene/sound_gene.qsf5
-rw-r--r--FPGA/sound_gene/sound_gene.qwsbin897 -> 2280 bytes
-rw-r--r--FPGA/sound_gene/sound_gene.tcl98
-rw-r--r--FPGA/tcl/7seg_pin.tcl (renamed from FPGA/top/7seg_pin.tcl)0
-rw-r--r--FPGA/tcl/bind_all.tcl (renamed from FPGA/bind_all.tcl)0
-rw-r--r--FPGA/tcl/commande_pin.tcl (renamed from FPGA/commande/commande_pin.tcl)0
-rw-r--r--FPGA/tcl/demo_io_pin.tcl (renamed from FPGA/top/demo_io_pin.tcl)0
-rw-r--r--FPGA/tcl/display_pin.tcl (renamed from FPGA/display/display_pin.tcl)0
-rw-r--r--FPGA/tcl/lcd_pin.tcl (renamed from FPGA/top/lcd_pin.tcl)0
-rw-r--r--FPGA/tcl/pwm.tcl (renamed from FPGA/pwm.tcl)0
-rw-r--r--FPGA/tcl/real_io_pin.tcl (renamed from FPGA/top/real_io_pin.tcl)0
-rw-r--r--FPGA/top/LCD_controller.bsf141
-rw-r--r--FPGA/top/clock_divider.bsf61
-rw-r--r--FPGA/top/codec_clock.bsf50
-rw-r--r--FPGA/top/codec_clock.qsf78
-rw-r--r--FPGA/top/codec_config.bsf75
-rw-r--r--FPGA/top/codec_dac.bsf113
-rw-r--r--FPGA/top/commande.bsf99
-rw-r--r--FPGA/top/dds_sinus.bsf68
-rw-r--r--FPGA/top/display.bsf120
-rw-r--r--FPGA/top/greybox_tmp/cbx_args.txt9
-rw-r--r--FPGA/top/lcd_message.bsf85
-rw-r--r--FPGA/top/lpm_compare0.bsf62
-rw-r--r--FPGA/top/lpm_counter0.bsf64
-rw-r--r--FPGA/top/lpm_counter1.bsf65
-rw-r--r--FPGA/top/lpm_counter1.qip0
-rw-r--r--FPGA/top/lpm_mux0.bsf82
-rw-r--r--FPGA/top/message.bsf43
-rw-r--r--FPGA/top/pwm.bsf64
-rw-r--r--FPGA/top/sound_gene.bsf113
-rw-r--r--FPGA/top/top.qsf54
-rw-r--r--FPGA/top/top.qwsbin0 -> 2997 bytes
-rw-r--r--FPGA/top/top.srf1
-rw-r--r--FPGA/top/top.tcl56
-rw-r--r--FPGA/top/useless.bsf71
-rw-r--r--FPGA/vhdl/LCD_message.bdf415
-rw-r--r--FPGA/vhdl/greybox_tmp/cbx_args.txt12
-rw-r--r--FPGA/vhdl/message.vhd.bak67
78 files changed, 1062 insertions, 3846 deletions
diff --git a/FPGA/LCD_message/LCD_controller.bsf b/FPGA/LCD_message/LCD_controller.bsf
deleted file mode 100644
index 9f6a194..0000000
--- a/FPGA/LCD_message/LCD_controller.bsf
+++ /dev/null
@@ -1,141 +0,0 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.1"))
22(symbol
23 (rect 16 16 232 256)
24 (text "LCD_controller" (rect 5 0 66 12)(font "Arial" ))
25 (text "inst" (rect 8 224 20 236)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 10 12)(font "Arial" ))
30 (text "clk" (rect 21 27 31 39)(font "Arial" ))
31 (line (pt 0 32)(pt 16 32)(line_width 1))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 24 12)(font "Arial" ))
37 (text "resetn" (rect 21 43 45 55)(font "Arial" ))
38 (line (pt 0 48)(pt 16 48)(line_width 1))
39 )
40 (port
41 (pt 0 64)
42 (input)
43 (text "en_250kHz" (rect 0 0 44 12)(font "Arial" ))
44 (text "en_250kHz" (rect 21 59 65 71)(font "Arial" ))
45 (line (pt 0 64)(pt 16 64)(line_width 1))
46 )
47 (port
48 (pt 0 80)
49 (input)
50 (text "mode[1..0]" (rect 0 0 41 12)(font "Arial" ))
51 (text "mode[1..0]" (rect 21 75 62 87)(font "Arial" ))
52 (line (pt 0 80)(pt 16 80)(line_width 3))
53 )
54 (port
55 (pt 0 96)
56 (input)
57 (text "char[7..0]" (rect 0 0 37 12)(font "Arial" ))
58 (text "char[7..0]" (rect 21 91 58 103)(font "Arial" ))
59 (line (pt 0 96)(pt 16 96)(line_width 3))
60 )
61 (port
62 (pt 0 112)
63 (input)
64 (text "address[6..0]" (rect 0 0 51 12)(font "Arial" ))
65 (text "address[6..0]" (rect 21 107 72 119)(font "Arial" ))
66 (line (pt 0 112)(pt 16 112)(line_width 3))
67 )
68 (port
69 (pt 0 128)
70 (input)
71 (text "write_char" (rect 0 0 41 12)(font "Arial" ))
72 (text "write_char" (rect 21 123 62 135)(font "Arial" ))
73 (line (pt 0 128)(pt 16 128)(line_width 1))
74 )
75 (port
76 (pt 0 144)
77 (input)
78 (text "write_address" (rect 0 0 55 12)(font "Arial" ))
79 (text "write_address" (rect 21 139 76 151)(font "Arial" ))
80 (line (pt 0 144)(pt 16 144)(line_width 1))
81 )
82 (port
83 (pt 0 160)
84 (input)
85 (text "D" (rect 0 0 7 12)(font "Arial" ))
86 (text "D" (rect 21 155 28 167)(font "Arial" ))
87 (line (pt 0 160)(pt 16 160)(line_width 1))
88 )
89 (port
90 (pt 0 176)
91 (input)
92 (text "C" (rect 0 0 7 12)(font "Arial" ))
93 (text "C" (rect 21 171 28 183)(font "Arial" ))
94 (line (pt 0 176)(pt 16 176)(line_width 1))
95 )
96 (port
97 (pt 0 192)
98 (input)
99 (text "B" (rect 0 0 5 12)(font "Arial" ))
100 (text "B" (rect 21 187 26 199)(font "Arial" ))