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author | Pacien TRAN-GIRARD | 2014-06-13 16:06:19 +0200 |
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committer | Pacien TRAN-GIRARD | 2014-06-13 16:06:19 +0200 |
commit | 70318492f3472ff2ec3b1735cf69a4eef1f6a51d (patch) | |
tree | 0f4243099ea9379bc164dc37a9fee3ab255f0f7e /FPGA/codec_clock/clock_divider.bsf | |
parent | d091bb2cb82f66d187df8f3aba6afcf4041b72ce (diff) | |
download | fpga-home-automation-70318492f3472ff2ec3b1735cf69a4eef1f6a51d.tar.gz |
Update project
Diffstat (limited to 'FPGA/codec_clock/clock_divider.bsf')
-rw-r--r-- | FPGA/codec_clock/clock_divider.bsf | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/FPGA/codec_clock/clock_divider.bsf b/FPGA/codec_clock/clock_divider.bsf new file mode 100644 index 0000000..de8cb37 --- /dev/null +++ b/FPGA/codec_clock/clock_divider.bsf | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | WARNING: Do NOT edit the input and output ports in this file in a text | ||
3 | editor if you plan to continue editing the block that represents it in | ||
4 | the Block Editor! File corruption is VERY likely to occur. | ||
5 | */ | ||
6 | /* | ||
7 | Copyright (C) 1991-2013 Altera Corporation | ||
8 | Your use of Altera Corporation's design tools, logic functions | ||
9 | and other software and tools, and its AMPP partner logic | ||
10 | functions, and any output files from any of the foregoing | ||
11 | (including device programming or simulation files), and any | ||
12 | associated documentation or information are expressly subject | ||
13 | to the terms and conditions of the Altera Program License | ||
14 | Subscription Agreement, Altera MegaCore Function License | ||
15 | Agreement, or other applicable license agreement, including, | ||
16 | without limitation, that your use is for the sole purpose of | ||
17 | programming logic devices manufactured by Altera and sold by | ||
18 | Altera or its authorized distributors. Please refer to the | ||
19 | applicable agreement for further details. | ||
20 | */ | ||
21 | (header "symbol" (version "1.1")) | ||
22 | (symbol | ||
23 | (rect 16 16 176 96) | ||
24 | (text "clock_divider" (rect 5 0 56 12)(font "Arial" )) | ||
25 | (text "inst" (rect 8 64 20 76)(font "Arial" )) | ||
26 | (port | ||
27 | (pt 0 32) | ||
28 | (input) | ||
29 | (text "clk" (rect 0 0 10 12)(font "Arial" )) | ||
30 | (text "clk" (rect 21 27 31 39)(font "Arial" )) | ||
31 | (line (pt 0 32)(pt 16 32)(line_width 1)) | ||
32 | ) | ||
33 | (port | ||
34 | (pt 0 48) | ||
35 | (input) | ||
36 | (text "resetn" (rect 0 0 24 12)(font "Arial" )) | ||
37 | (text "resetn" (rect 21 43 45 55)(font "Arial" )) | ||
38 | (line (pt 0 48)(pt 16 48)(line_width 1)) | ||
39 | ) | ||
40 | (port | ||
41 | (pt 160 32) | ||
42 | (output) | ||
43 | (text "en_user" (rect 0 0 33 12)(font "Arial" )) | ||
44 | (text "en_user" (rect 106 27 139 39)(font "Arial" )) | ||
45 | (line (pt 160 32)(pt 144 32)(line_width 1)) | ||
46 | ) | ||
47 | (parameter | ||
48 | "board_frequency" | ||
49 | "50000000.0" | ||
50 | "" | ||
51 | (type "PARAMETER_SIGNED_FLOAT") ) | ||
52 | (parameter | ||
53 | "user_frequency" | ||
54 | "4.0" | ||
55 | "" | ||
56 | (type "PARAMETER_SIGNED_FLOAT") ) | ||
57 | (drawing | ||
58 | (rectangle (rect 16 16 144 64)(line_width 1)) | ||
59 | ) | ||
60 | (annotation_block (parameter)(rect 176 -64 276 16)) | ||
61 | ) | ||