Add display module

1 files changed, 118 insertions, 0 deletions

diff --git a/FPGA/display/display.qsf b/FPGA/display/display.qsf
new file mode 100644
index 0000000..4a3d072
--- /dev/null
+++ b/FPGA/display/display.qsf
@@ -0,0 +1,118 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
+# Date created = 21:12:46  April 11, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#               display_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#               assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C35F672C6
+set_global_assignment -name TOP_LEVEL_ENTITY display
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:12:46  APRIL 11, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_location_assignment PIN_AE14 -to speed[1]
+set_location_assignment PIN_P25 -to speed[0]
+set_location_assignment PIN_N26 -to fan_auto
+set_location_assignment PIN_N25 -to alarm_user
+set_location_assignment PIN_AF10 -to hex0[0]
+set_location_assignment PIN_AB12 -to hex0[1]
+set_location_assignment PIN_AC12 -to hex0[2]
+set_location_assignment PIN_AD11 -to hex0[3]
+set_location_assignment PIN_AE11 -to hex0[4]
+set_location_assignment PIN_V14 -to hex0[5]
+set_location_assignment PIN_V13 -to hex0[6]
+set_location_assignment PIN_V20 -to hex1[0]
+set_location_assignment PIN_V21 -to hex1[1]
+set_location_assignment PIN_W21 -to hex1[2]
+set_location_assignment PIN_Y22 -to hex1[3]
+set_location_assignment PIN_AA24 -to hex1[4]
+set_location_assignment PIN_AA23 -to hex1[5]
+set_location_assignment PIN_AB24 -to hex1[6]
+set_location_assignment PIN_AB23 -to hex2[0]
+set_location_assignment PIN_V22 -to hex2[1]
+set_location_assignment PIN_AC25 -to hex2[2]
+set_location_assignment PIN_AC26 -to hex2[3]
+set_location_assignment PIN_AB26 -to hex2[4]
+set_location_assignment PIN_AB25 -to hex2[5]
+set_location_assignment PIN_Y24 -to hex2[6]
+set_location_assignment PIN_Y23 -to hex3[0]
+set_location_assignment PIN_AA25 -to hex3[1]
+set_location_assignment PIN_AA26 -to hex3[2]
+set_location_assignment PIN_Y26 -to hex3[3]
+set_location_assignment PIN_Y25 -to hex3[4]
+set_location_assignment PIN_U22 -to hex3[5]
+set_location_assignment PIN_W24 -to hex3[6]
+set_location_assignment PIN_U9 -to hex4[0]
+set_location_assignment PIN_U1 -to hex4[1]
+set_location_assignment PIN_U2 -to hex4[2]
+set_location_assignment PIN_T4 -to hex4[3]
+set_location_assignment PIN_R7 -to hex4[4]
+set_location_assignment PIN_R6 -to hex4[5]
+set_location_assignment PIN_T3 -to hex4[6]
+set_location_assignment PIN_T2 -to hex5[0]
+set_location_assignment PIN_P6 -to hex5[1]
+set_location_assignment PIN_P7 -to hex5[2]
+set_location_assignment PIN_T9 -to hex5[3]
+set_location_assignment PIN_R5 -to hex5[4]
+set_location_assignment PIN_R4 -to hex5[5]
+set_location_assignment PIN_R3 -to hex5[6]
+set_location_assignment PIN_R2 -to hex6[0]
+set_location_assignment PIN_P4 -to hex6[1]
+set_location_assignment PIN_P3 -to hex6[2]
+set_location_assignment PIN_M2 -to hex6[3]
+set_location_assignment PIN_M3 -to hex6[4]
+set_location_assignment PIN_M5 -to hex6[5]
+set_location_assignment PIN_M4 -to hex6[6]
+set_location_assignment PIN_L3 -to hex7[0]
+set_location_assignment PIN_L2 -to hex7[1]
+set_location_assignment PIN_L9 -to hex7[2]
+set_location_assignment PIN_L6 -to hex7[3]
+set_location_assignment PIN_L7 -to hex7[4]
+set_location_assignment PIN_P9 -to hex7[5]
+set_location_assignment PIN_N9 -to hex7[6]
+set_global_assignment -name BDF_FILE display.bdf
+set_global_assignment -name VHDL_FILE ../vhdl/seven_segment_decoder.vhd
+set_global_assignment -name TCL_SCRIPT_FILE display_pin.tcl
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file