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authorPacien TRAN-GIRARD2014-06-13 16:06:19 +0200
committerPacien TRAN-GIRARD2014-06-13 16:06:19 +0200
commit70318492f3472ff2ec3b1735cf69a4eef1f6a51d (patch)
tree0f4243099ea9379bc164dc37a9fee3ab255f0f7e /FPGA/top
parentd091bb2cb82f66d187df8f3aba6afcf4041b72ce (diff)
downloadfpga-home-automation-70318492f3472ff2ec3b1735cf69a4eef1f6a51d.tar.gz
Update project
Diffstat (limited to 'FPGA/top')
-rw-r--r--FPGA/top/LCD_controller.bsf141
-rw-r--r--FPGA/top/clock_divider.bsf61
-rw-r--r--FPGA/top/codec_clock.bsf50
-rw-r--r--FPGA/top/codec_clock.qsf78
-rw-r--r--FPGA/top/codec_config.bsf75
-rw-r--r--FPGA/top/codec_dac.bsf113
-rw-r--r--FPGA/top/dds_sinus.bsf68
-rw-r--r--FPGA/top/display.bsf83
-rw-r--r--FPGA/top/greybox_tmp/cbx_args.txt9
-rw-r--r--FPGA/top/lcd_message.bsf85
-rw-r--r--FPGA/top/lpm_compare0.bsf62
-rw-r--r--FPGA/top/lpm_counter0.bsf64
-rw-r--r--FPGA/top/lpm_counter1.bsf65
-rw-r--r--FPGA/top/lpm_counter1.qip0
-rw-r--r--FPGA/top/lpm_mux0.bsf82
-rw-r--r--FPGA/top/message.bsf43
-rw-r--r--FPGA/top/pwm.bsf64
-rw-r--r--FPGA/top/sound_gene.bsf113
-rw-r--r--FPGA/top/top.bdf1015
-rw-r--r--FPGA/top/top.bsf232
-rw-r--r--FPGA/top/top.qsf57
-rw-r--r--FPGA/top/top.tcl212
-rw-r--r--FPGA/top/useless.bsf71
23 files changed, 2711 insertions, 132 deletions
diff --git a/FPGA/top/LCD_controller.bsf b/FPGA/top/LCD_controller.bsf
new file mode 100644
index 0000000..9f6a194
--- /dev/null
+++ b/FPGA/top/LCD_controller.bsf
@@ -0,0 +1,141 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.1"))
22(symbol
23 (rect 16 16 232 256)
24 (text "LCD_controller" (rect 5 0 66 12)(font "Arial" ))
25 (text "inst" (rect 8 224 20 236)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 10 12)(font "Arial" ))
30 (text "clk" (rect 21 27 31 39)(font "Arial" ))
31 (line (pt 0 32)(pt 16 32)(line_width 1))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 24 12)(font "Arial" ))
37 (text "resetn" (rect 21 43 45 55)(font "Arial" ))
38 (line (pt 0 48)(pt 16 48)(line_width 1))
39 )
40 (port
41 (pt 0 64)
42 (input)
43 (text "en_250kHz" (rect 0 0 44 12)(font "Arial" ))
44 (text "en_250kHz" (rect 21 59 65 71)(font "Arial" ))
45 (line (pt 0 64)(pt 16 64)(line_width 1))
46 )
47 (port
48 (pt 0 80)
49 (input)
50 (text "mode[1..0]" (rect 0 0 41 12)(font "Arial" ))
51 (text "mode[1..0]" (rect 21 75 62 87)(font "Arial" ))
52 (line (pt 0 80)(pt 16 80)(line_width 3))
53 )
54 (port
55 (pt 0 96)
56 (input)
57 (text "char[7..0]" (rect 0 0 37 12)(font "Arial" ))
58 (text "char[7..0]" (rect 21 91 58 103)(font "Arial" ))
59 (line (pt 0 96)(pt 16 96)(line_width 3))
60 )
61 (port
62 (pt 0 112)
63 (input)
64 (text "address[6..0]" (rect 0 0 51 12)(font "Arial" ))
65 (text "address[6..0]" (rect 21 107 72 119)(font "Arial" ))
66 (line (pt 0 112)(pt 16 112)(line_width 3))
67 )
68 (port
69 (pt 0 128)
70 (input)
71 (text "write_char" (rect 0 0 41 12)(font "Arial" ))
72 (text "write_char" (rect 21 123 62 135)(font "Arial" ))
73 (line (pt 0 128)(pt 16 128)(line_width 1))
74 )
75 (port
76 (pt 0 144)
77 (input)
78 (text "write_address" (rect 0 0 55 12)(font "Arial" ))
79 (text "write_address" (rect 21 139 76 151)(font "Arial" ))
80 (line (pt 0 144)(pt 16 144)(line_width 1))
81 )
82 (port
83 (pt 0 160)
84 (input)
85 (text "D" (rect 0 0 7 12)(font "Arial" ))
86 (text "D" (rect 21 155 28 167)(font "Arial" ))
87 (line (pt 0 160)(pt 16 160)(line_width 1))
88 )
89 (port
90 (pt 0 176)
91 (input)
92 (text "C" (rect 0 0 7 12)(font "Arial" ))
93 (text "C" (rect 21 171 28 183)(font "Arial" ))
94 (line (pt 0 176)(pt 16 176)(line_width 1))
95 )
96 (port
97 (pt 0 192)
98 (input)
99 (text "B" (rect 0 0 5 12)(font "Arial" ))
100 (text "B" (rect 21 187 26 199)(font "Arial" ))
101 (line (pt 0 192)(pt 16 192)(line_width 1))
102 )
103 (port
104 (pt 216 32)
105 (output)
106 (text "ready" (rect 0 0 23 12)(font "Arial" ))
107 (text "ready" (rect 172 27 195 39)(font "Arial" ))
108 (line (pt 216 32)(pt 200 32)(line_width 1))
109 )
110 (port
111 (pt 216 64)
112 (output)
113 (text "LCD_RS" (rect 0 0 40 12)(font "Arial" ))
114 (text "LCD_RS" (rect 155 59 195 71)(font "Arial" ))
115 (line (pt 216 64)(pt 200 64)(line_width 1))
116 )
117 (port
118 (pt 216 80)
119 (output)
120 (text "LCD_RW" (rect 0 0 44 12)(font "Arial" ))
121 (text "LCD_RW" (rect 151 75 195 87)(font "Arial" ))
122 (line (pt 216 80)(pt 200 80)(line_width 1))
123 )
124 (port
125 (pt 216 96)
126 (output)
127 (text "LCD_EN" (rect 0 0 40 12)(font "Arial" ))
128 (text "LCD_EN" (rect 155 91 195 103)(font "Arial" ))
129 (line (pt 216 96)(pt 200 96)(line_width 1))
130 )
131 (port
132 (pt 216 48)
133 (bidir)
134 (text "LCD_data[7..0]" (rect 0 0 62 12)(font "Arial" ))
135 (text "LCD_data[7..0]" (rect 133 43 195 55)(font "Arial" ))
136 (line (pt 216 48)(pt 200 48)(line_width 3))
137 )
138 (drawing
139 (rectangle (rect 16 16 200 224)(line_width 1))
140 )
141)
diff --git a/FPGA/top/clock_divider.bsf b/FPGA/top/clock_divider.bsf
new file mode 100644
index 0000000..de8cb37
--- /dev/null
+++ b/FPGA/top/clock_divider.bsf
@@ -0,0 +1,61 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.1"))
22(symbol
23 (rect 16 16 176 96)
24 (text "clock_divider" (rect 5 0 56 12)(font "Arial" ))
25 (text "inst" (rect 8 64 20 76)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 10 12)(font "Arial" ))
30 (text "clk" (rect 21 27 31 39)(font "Arial" ))
31 (line (pt 0 32)(pt 16 32)(line_width 1))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 24 12)(font "Arial" ))
37 (text "resetn" (rect 21 43 45 55)(font "Arial" ))
38 (line (pt 0 48)(pt 16 48)(line_width 1))
39 )
40 (port
41 (pt 160 32)
42 (output)
43 (text "en_user" (rect 0 0 33 12)(font "Arial" ))
44 (text "en_user" (rect 106 27 139 39)(font "Arial" ))