Update project

1 files changed, 2 insertions, 2 deletions

diff --git a/FPGA/vhdl/dds_sinus.vhd b/FPGA/vhdl/dds_sinus.vhd
index d47f290..1de67d8 100644
--- a/FPGA/vhdl/dds_sinus.vhd
+++ b/FPGA/vhdl/dds_sinus.vhd
@@ -37,14 +37,14 @@ entity dds_sinus is
   port (    
     resetn      : in  std_logic;
     clk         : in  std_logic;
-    en          : in  std_logic;
-    incr_step   : in  std_logic_vector(M-1      downto 0);
+    en          : in  std_logic;    
     dds_out     : out std_logic_vector(N_data-1 downto 0)
     );
 end dds_sinus;
 
 architecture RTL of dds_sinus is

   constant amplitude   : positive :=2**(N_data-1)-1;

+  constant incr_step   : std_logic_vector(M-1 downto 0):= (0=>'1', others => '0');

   constant N_adr_ROM   : positive := M-2;
   constant middle      : unsigned (N_data-1 downto 0) := to_unsigned(2**(dds_out'length-1),dds_out'length); --(N_data-1=>'1', others => '0');