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-rw-r--r--FPGA/pwm/greybox_tmp/cbx_args.txt7
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v52
-rw-r--r--FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v51
-rw-r--r--FPGA/pwm/lpm_counter0.bsf64
-rw-r--r--FPGA/pwm/lpm_counter0.cmp23
-rw-r--r--FPGA/pwm/lpm_counter0.qip5
-rw-r--r--FPGA/pwm/lpm_counter0.vhd130
-rw-r--r--FPGA/pwm/pwm.qsf1
-rw-r--r--FPGA/pwm/pwm.qwsbin1406 -> 2168 bytes
-rw-r--r--FPGA/pwm/pwm.tcl88
10 files changed, 82 insertions, 339 deletions
diff --git a/FPGA/pwm/greybox_tmp/cbx_args.txt b/FPGA/pwm/greybox_tmp/cbx_args.txt
deleted file mode 100644
index 662f251..0000000
--- a/FPGA/pwm/greybox_tmp/cbx_args.txt
+++ /dev/null
@@ -1,7 +0,0 @@
1LPM_REPRESENTATION=UNSIGNED
2LPM_TYPE=LPM_COMPARE
3LPM_WIDTH=23
4DEVICE_FAMILY="Cyclone II"
5dataa
6datab
7alb
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
deleted file mode 100644
index 90c1893..0000000
--- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgbt9.v
+++ /dev/null
@@ -1,52 +0,0 @@
1//lpm_mux CBX_SINGLE_OUTPUT_FILE="ON" LPM_SIZE=4 LPM_TYPE="LPM_MUX" LPM_WIDTH=1 LPM_WIDTHS=2 data result sel
2//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ VERSION_END
3// synthesis VERILOG_INPUT_VERSION VERILOG_2001
4// altera message_off 10463
5
6
7
8// Copyright (C) 1991-2013 Altera Corporation
9// Your use of Altera Corporation's design tools, logic functions
10// and other software and tools, and its AMPP partner logic
11// functions, and any output files from any of the foregoing
12// (including device programming or simulation files), and any
13// associated documentation or information are expressly subject
14// to the terms and conditions of the Altera Program License
15// Subscription Agreement, Altera MegaCore Function License
16// Agreement, or other applicable license agreement, including,
17// without limitation, that your use is for the sole purpose of
18// programming logic devices manufactured by Altera and sold by
19// Altera or its authorized distributors. Please refer to the
20// applicable agreement for further details.
21
22
23
24//synthesis_resources = lpm_mux 1
25//synopsys translate_off
26`timescale 1 ps / 1 ps
27//synopsys translate_on
28module mgbt9
29 (
30 data,
31 result,
32 sel) /* synthesis synthesis_clearbox=1 */;
33 input [3:0] data;
34 output [0:0] result;
35 input [1:0] sel;
36
37 wire [0:0] wire_mgl_prim1_result;
38
39 lpm_mux mgl_prim1
40 (
41 .data(data),
42 .result(wire_mgl_prim1_result),
43 .sel(sel));
44 defparam
45 mgl_prim1.lpm_size = 4,
46 mgl_prim1.lpm_type = "LPM_MUX",
47 mgl_prim1.lpm_width = 1,
48 mgl_prim1.lpm_widths = 2;
49 assign
50 result = wire_mgl_prim1_result;
51endmodule //mgbt9
52//VALID FILE
diff --git a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v b/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
deleted file mode 100644
index 8fab5c3..0000000
--- a/FPGA/pwm/greybox_tmp/greybox_tmp/mgtbb.v
+++ /dev/null
@@ -1,51 +0,0 @@
1//lpm_compare CBX_SINGLE_OUTPUT_FILE="ON" LPM_REPRESENTATION="UNSIGNED" LPM_TYPE="LPM_COMPARE" LPM_WIDTH=23 alb dataa datab
2//VERSION_BEGIN 13.0 cbx_mgl 2013:06:12:18:04:42:SJ cbx_stratixii 2013:06:12:18:04:00:SJ cbx_util_mgl 2013:06:12:18:04:00:SJ VERSION_END
3// synthesis VERILOG_INPUT_VERSION VERILOG_2001
4// altera message_off 10463
5
6
7
8// Copyright (C) 1991-2013 Altera Corporation
9// Your use of Altera Corporation's design tools, logic functions
10// and other software and tools, and its AMPP partner logic
11// functions, and any output files from any of the foregoing
12// (including device programming or simulation files), and any
13// associated documentation or information are expressly subject
14// to the terms and conditions of the Altera Program License
15// Subscription Agreement, Altera MegaCore Function License
16// Agreement, or other applicable license agreement, including,
17// without limitation, that your use is for the sole purpose of
18// programming logic devices manufactured by Altera and sold by
19// Altera or its authorized distributors. Please refer to the
20// applicable agreement for further details.
21
22
23
24//synthesis_resources = lpm_compare 1
25//synopsys translate_off
26`timescale 1 ps / 1 ps
27//synopsys translate_on
28module mgtbb
29 (
30 alb,
31 dataa,
32 datab) /* synthesis synthesis_clearbox=1 */;
33 output alb;
34 input [22:0] dataa;
35 input [22:0] datab;
36
37 wire wire_mgl_prim1_alb;
38
39 lpm_compare mgl_prim1
40 (
41 .alb(wire_mgl_prim1_alb),
42 .dataa(dataa),
43 .datab(datab));
44 defparam
45 mgl_prim1.lpm_representation = "UNSIGNED",
46 mgl_prim1.lpm_type = "LPM_COMPARE",
47 mgl_prim1.lpm_width = 23;
48 assign
49 alb = wire_mgl_prim1_alb;
50endmodule //mgtbb
51//VALID FILE
diff --git a/FPGA/pwm/lpm_counter0.bsf b/FPGA/pwm/lpm_counter0.bsf
deleted file mode 100644
index 5cc02c4..0000000
--- a/FPGA/pwm/lpm_counter0.bsf
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.2"))
22(symbol
23 (rect 0 0 144 96)
24 (text "lpm_counter0" (rect 33 0 129 16)(font "Arial" (font_size 10)))
25 (text "inst" (rect 8 81 26 92)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clock" (rect 0 0 31 13)(font "Arial" (font_size 8)))
30 (text "clock" (rect 26 26 51 38)(font "Arial" (font_size 8)))
31 (line (pt 0 32)(pt 16 32))
32 )
33 (port
34 (pt 80 96)
35 (input)
36 (text "aclr" (rect 0 0 13 22)(font "Arial" (font_size 8))(vertical))
37 (text "aclr" (rect 74 57 86 75)(font "Arial" (font_size 8))(vertical))
38 (line (pt 80 96)(pt 80 80))
39 )
40 (port
41 (pt 144 40)
42 (output)
43 (text "q[18..0]" (rect 0 0 43 13)(font "Arial" (font_size 8)))
44 (text "q[18..0]" (rect 89 34 126 46)(font "Arial" (font_size 8)))
45 (line (pt 144 40)(pt 128 40)(line_width 3))
46 )
47 (drawing
48 (text "up counter" (rect 84 23 214 56)(font "Arial" ))
49 (line (pt 16 16)(pt 16 80))
50 (line (pt 16 16)(pt 128 16))
51 (line (pt 16 80)(pt 128 80))
52 (line (pt 128 16)(pt 128 80))
53 (line (pt 0 0)(pt 146 0))
54 (line (pt 146 0)(pt 146 98))
55 (line (pt 0 98)(pt 146 98))
56 (line (pt 0 0)(pt 0 98))
57 (line (pt 16 26)(pt 22 32))
58 (line (pt 22 32)(pt 16 38))
59 (line (pt 0 0)(pt 0 0))
60 (line (pt 0 0)(pt 0 0))
61 (line (pt 0 0)(pt 0 0))
62 (line (pt 0 0)(pt 0 0))
63 )
64)
diff --git a/FPGA/pwm/lpm_counter0.cmp b/FPGA/pwm/lpm_counter0.cmp
deleted file mode 100644
index f505116..0000000
--- a/FPGA/pwm/lpm_counter0.cmp
+++ /dev/null
@@ -1,23 +0,0 @@
1--Copyright (C) 1991-2013 Altera Corporation
2--Your use of Altera Corporation's design tools, logic functions
3--and other software and tools, and its AMPP partner logic
4--functions, and any output files from any of the foregoing
5--(including device programming or simulation files), and any
6--associated documentation or information are expressly subject
7--to the terms and conditions of the Altera Program License
8--Subscription Agreement, Altera MegaCore Function License
9--Agreement, or other applicable license agreement, including,
10--without limitation, that your use is for the sole purpose of
11--programming logic devices manufactured by Altera and sold by
12--Altera or its authorized distributors. Please refer to the
13--applicable agreement for further details.
14
15
16component lpm_counter0
17 PORT
18 (
19 aclr : IN STD_LOGIC ;
20 clock : IN STD_LOGIC ;
21 q : OUT STD_LOGIC_VECTOR (18 DOWNTO 0)
22 );
23end component;
diff --git a/FPGA/pwm/lpm_counter0.qip b/FPGA/pwm/lpm_counter0.qip
deleted file mode 100644
index f7b47d7..0000000
--- a/FPGA/pwm/lpm_counter0.qip
+++ /dev/null
@@ -1,5 +0,0 @@
1set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
2set_global_assignment -name IP_TOOL_VERSION "13.0"
3set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"]