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-rw-r--r--FPGA/sound_gene/clock_divider.bsf61
-rw-r--r--FPGA/sound_gene/codec_clock.bsf50
-rw-r--r--FPGA/sound_gene/codec_config.bsf75
-rw-r--r--FPGA/sound_gene/codec_dac.bsf113
-rw-r--r--FPGA/sound_gene/dds_sinus.bsf68
-rw-r--r--FPGA/sound_gene/sound_gene.bdf927
-rw-r--r--FPGA/sound_gene/sound_gene.bsf113
-rw-r--r--FPGA/sound_gene/sound_gene.qpf30
-rw-r--r--FPGA/sound_gene/sound_gene.qsf85
-rw-r--r--FPGA/sound_gene/sound_gene.qwsbin0 -> 897 bytes
10 files changed, 1522 insertions, 0 deletions
diff --git a/FPGA/sound_gene/clock_divider.bsf b/FPGA/sound_gene/clock_divider.bsf
new file mode 100644
index 0000000..de8cb37
--- /dev/null
+++ b/FPGA/sound_gene/clock_divider.bsf
@@ -0,0 +1,61 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.1"))
22(symbol
23 (rect 16 16 176 96)
24 (text "clock_divider" (rect 5 0 56 12)(font "Arial" ))
25 (text "inst" (rect 8 64 20 76)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 10 12)(font "Arial" ))
30 (text "clk" (rect 21 27 31 39)(font "Arial" ))
31 (line (pt 0 32)(pt 16 32)(line_width 1))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 24 12)(font "Arial" ))
37 (text "resetn" (rect 21 43 45 55)(font "Arial" ))
38 (line (pt 0 48)(pt 16 48)(line_width 1))
39 )
40 (port
41 (pt 160 32)
42 (output)
43 (text "en_user" (rect 0 0 33 12)(font "Arial" ))
44 (text "en_user" (rect 106 27 139 39)(font "Arial" ))
45 (line (pt 160 32)(pt 144 32)(line_width 1))
46 )
47 (parameter
48 "board_frequency"
49 "50000000.0"
50 ""
51 (type "PARAMETER_SIGNED_FLOAT") )
52 (parameter
53 "user_frequency"
54 "4.0"
55 ""
56 (type "PARAMETER_SIGNED_FLOAT") )
57 (drawing
58 (rectangle (rect 16 16 144 64)(line_width 1))
59 )
60 (annotation_block (parameter)(rect 176 -64 276 16))
61)
diff --git a/FPGA/sound_gene/codec_clock.bsf b/FPGA/sound_gene/codec_clock.bsf
new file mode 100644
index 0000000..c112470
--- /dev/null
+++ b/FPGA/sound_gene/codec_clock.bsf
@@ -0,0 +1,50 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.2"))
22(symbol
23 (rect 16 16 152 112)
24 (text "codec_clock" (rect 5 0 76 13)(font "Arial" (font_size 8)))
25 (text "inst" (rect 8 81 26 92)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
30 (text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
31 (line (pt 0 32)(pt 16 32))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
37 (text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
38 (line (pt 0 48)(pt 16 48))
39 )
40 (port
41 (pt 136 32)
42 (output)
43 (text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8)))
44 (text "xti_mclk" (rect 67 27 115 40)(font "Arial" (font_size 8)))
45 (line (pt 136 32)(pt 120 32))
46 )
47 (drawing
48 (rectangle (rect 16 16 120 80))
49 )
50)
diff --git a/FPGA/sound_gene/codec_config.bsf b/FPGA/sound_gene/codec_config.bsf
new file mode 100644
index 0000000..b2b4d9f
--- /dev/null
+++ b/FPGA/sound_gene/codec_config.bsf
@@ -0,0 +1,75 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by
18Altera or its authorized distributors. Please refer to the
19applicable agreement for further details.
20*/
21(header "symbol" (version "1.1"))
22(symbol
23 (rect 16 16 184 128)
24 (text "codec_config" (rect 5 0 58 12)(font "Arial" ))
25 (text "inst" (rect 8 96 20 108)(font "Arial" ))
26 (port
27 (pt 0 32)
28 (input)
29 (text "clk" (rect 0 0 10 12)(font "Arial" ))
30 (text "clk" (rect 21 27 31 39)(font "Arial" ))
31 (line (pt 0 32)(pt 16 32)(line_width 1))
32 )
33 (port
34 (pt 0 48)
35 (input)
36 (text "resetn" (rect 0 0 24 12)(font "Arial" ))
37 (text "resetn" (rect 21 43 45 55)(font "Arial" ))
38 (line (pt 0 48)(pt 16 48)(line_width 1))
39 )
40 (port
41 (pt 168 32)
42 (output)
43 (text "end_config" (rect 0 0 43 12)(font "Arial" ))
44 (text "end_config" (rect 104 27 147 39)(font "Arial" ))
45 (line (pt 168 32)(pt 152 32)(line_width 1))
46 )
47 (port
48 (pt 168 48)
49 (output)
50 (text "i2c_scl" (rect 0 0 27 12)(font "Arial" ))
51 (text "i2c_scl" (rect 120 43 147 55)(font "Arial" ))
52 (line (pt 168 48)(pt 152 48)(line_width 1))
53 )
54 (port
55 (pt 168 64)
56 (bidir)
57 (text "i2c_sda" (rect 0 0 30 12)(font "Arial" ))
58 (text "i2c_sda" (rect 117 59 147 71)(font "Arial" ))
59 (line (pt 168 64)(pt 152 64)(line_width 1))
60 )
61 (parameter
62 "system_frequency"
63 "50000000.0"
64 ""
65 (type "PARAMETER_SIGNED_FLOAT") )
66 (parameter
67 "i2c_rate"
68 "20000.0"
69 ""
70 (type "PARAMETER_SIGNED_FLOAT") )
71 (drawing
72 (rectangle (rect 16 16 152 96)(line_width 1))
73 )
74 (annotation_block (parameter)(rect 184 -64 284 16))
75)
diff --git a/FPGA/sound_gene/codec_dac.bsf b/FPGA/sound_gene/codec_dac.bsf
new file mode 100644
index 0000000..695e7d0
--- /dev/null
+++ b/FPGA/sound_gene/codec_dac.bsf
@@ -0,0 +1,113 @@
1/*
2WARNING: Do NOT edit the input and output ports in this file in a text
3editor if you plan to continue editing the block that represents it in
4the Block Editor! File corruption is VERY likely to occur.
5*/
6/*
7Copyright (C) 1991-2013 Altera Corporation
8Your use of Altera Corporation's design tools, logic functions
9and other software and tools, and its AMPP partner logic
10functions, and any output files from any of the foregoing
11(including device programming or simulation files), and any
12associated documentation or information are expressly subject
13to the terms and conditions of the Altera Program License
14Subscription Agreement, Altera MegaCore Function License
15Agreement, or other applicable license agreement, including,
16without limitation, that your use is for the sole purpose of
17programming logic devices manufactured by Altera and sold by