10 files changed, 1522 insertions, 0 deletions

diff --git a/FPGA/sound_gene/clock_divider.bsf b/FPGA/sound_gene/clock_divider.bsf
new file mode 100644
index 0000000..de8cb37
--- /dev/null
+++ b/FPGA/sound_gene/clock_divider.bsf
@@ -0,0 +1,61 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+        (rect 16 16 176 96)
+        (text "clock_divider" (rect 5 0 56 12)(font "Arial" ))
+        (text "inst" (rect 8 64 20 76)(font "Arial" ))
+        (port
+                (pt 0 32)
+                (input)
+                (text "clk" (rect 0 0 10 12)(font "Arial" ))
+                (text "clk" (rect 21 27 31 39)(font "Arial" ))
+                (line (pt 0 32)(pt 16 32)(line_width 1))
+        )
+        (port
+                (pt 0 48)
+                (input)
+                (text "resetn" (rect 0 0 24 12)(font "Arial" ))
+                (text "resetn" (rect 21 43 45 55)(font "Arial" ))
+                (line (pt 0 48)(pt 16 48)(line_width 1))
+        )
+        (port
+                (pt 160 32)
+                (output)
+                (text "en_user" (rect 0 0 33 12)(font "Arial" ))
+                (text "en_user" (rect 106 27 139 39)(font "Arial" ))
+                (line (pt 160 32)(pt 144 32)(line_width 1))
+        )
+        (parameter
+                "board_frequency"
+                "50000000.0"
+                ""
+                (type "PARAMETER_SIGNED_FLOAT") )
+        (parameter
+                "user_frequency"
+                "4.0"
+                ""
+                (type "PARAMETER_SIGNED_FLOAT") )
+        (drawing
+                (rectangle (rect 16 16 144 64)(line_width 1))
+        )
+        (annotation_block (parameter)(rect 176 -64 276 16))
+)
diff --git a/FPGA/sound_gene/codec_clock.bsf b/FPGA/sound_gene/codec_clock.bsf
new file mode 100644
index 0000000..c112470
--- /dev/null
+++ b/FPGA/sound_gene/codec_clock.bsf
@@ -0,0 +1,50 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+        (rect 16 16 152 112)
+        (text "codec_clock" (rect 5 0 76 13)(font "Arial" (font_size 8)))
+        (text "inst" (rect 8 81 26 92)(font "Arial" ))
+        (port
+                (pt 0 32)
+                (input)
+                (text "clk" (rect 0 0 18 13)(font "Arial" (font_size 8)))
+                (text "clk" (rect 21 27 39 40)(font "Arial" (font_size 8)))
+                (line (pt 0 32)(pt 16 32))
+        )
+        (port
+                (pt 0 48)
+                (input)
+                (text "resetn" (rect 0 0 36 13)(font "Arial" (font_size 8)))
+                (text "resetn" (rect 21 43 57 56)(font "Arial" (font_size 8)))
+                (line (pt 0 48)(pt 16 48))
+        )
+        (port
+                (pt 136 32)
+                (output)
+                (text "xti_mclk" (rect 0 0 48 13)(font "Arial" (font_size 8)))
+                (text "xti_mclk" (rect 67 27 115 40)(font "Arial" (font_size 8)))
+                (line (pt 136 32)(pt 120 32))
+        )
+        (drawing
+                (rectangle (rect 16 16 120 80))
+        )
+)
diff --git a/FPGA/sound_gene/codec_config.bsf b/FPGA/sound_gene/codec_config.bsf
new file mode 100644
index 0000000..b2b4d9f
--- /dev/null
+++ b/FPGA/sound_gene/codec_config.bsf
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+        (rect 16 16 184 128)
+        (text "codec_config" (rect 5 0 58 12)(font "Arial" ))
+        (text "inst" (rect 8 96 20 108)(font "Arial" ))
+        (port
+                (pt 0 32)
+                (input)
+                (text "clk" (rect 0 0 10 12)(font "Arial" ))
+                (text "clk" (rect 21 27 31 39)(font "Arial" ))
+                (line (pt 0 32)(pt 16 32)(line_width 1))
+        )
+        (port
+                (pt 0 48)
+                (input)
+                (text "resetn" (rect 0 0 24 12)(font "Arial" ))
+                (text "resetn" (rect 21 43 45 55)(font "Arial" ))
+                (line (pt 0 48)(pt 16 48)(line_width 1))
+        )
+        (port
+                (pt 168 32)
+                (output)
+                (text "end_config" (rect 0 0 43 12)(font "Arial" ))
+                (text "end_config" (rect 104 27 147 39)(font "Arial" ))
+                (line (pt 168 32)(pt 152 32)(line_width 1))
+        )
+        (port
+                (pt 168 48)
+                (output)
+                (text "i2c_scl" (rect 0 0 27 12)(font "Arial" ))
+                (text "i2c_scl" (rect 120 43 147 55)(font "Arial" ))
+                (line (pt 168 48)(pt 152 48)(line_width 1))
+        )
+        (port
+                (pt 168 64)
+                (bidir)
+                (text "i2c_sda" (rect 0 0 30 12)(font "Arial" ))
+                (text "i2c_sda" (rect 117 59 147 71)(font "Arial" ))
+                (line (pt 168 64)(pt 152 64)(line_width 1))
+        )
+        (parameter
+                "system_frequency"
+                "50000000.0"
+                ""
+                (type "PARAMETER_SIGNED_FLOAT") )
+        (parameter
+                "i2c_rate"
+                "20000.0"
+                ""
+                (type "PARAMETER_SIGNED_FLOAT") )
+        (drawing
+                (rectangle (rect 16 16 152 96)(line_width 1))
+        )
+        (annotation_block (parameter)(rect 184 -64 284 16))
+)
diff --git a/FPGA/sound_gene/codec_dac.bsf b/FPGA/sound_gene/codec_dac.bsf
new file mode 100644
index 0000000..695e7d0
--- /dev/null
+++ b/FPGA/sound_gene/codec_dac.bsf
@@ -0,0 +1,113 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by