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Diffstat (limited to 'FPGA/vhdl/seven_segment_decoder.vhd')
-rw-r--r-- | FPGA/vhdl/seven_segment_decoder.vhd | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/FPGA/vhdl/seven_segment_decoder.vhd b/FPGA/vhdl/seven_segment_decoder.vhd new file mode 100644 index 0000000..8852319 --- /dev/null +++ b/FPGA/vhdl/seven_segment_decoder.vhd | |||
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1 | ------------------------------------------- | ||
2 | -- decodeur 7 segments | ||
3 | ------------------------------------------- | ||
4 | -- ESIEE | ||
5 | -- Creation : A. Exertier, novembre 2004 | ||
6 | -- Modification : A. Exertier, decembre 2011 | ||
7 | ------------------------------------------- | ||
8 | |||
9 | library ieee; | ||
10 | use ieee.std_logic_1164.all; | ||
11 | --------------------------------------------------- | ||
12 | -- Parametre generique | ||
13 | --------------------------------------------------- | ||
14 | -- active_low : true => segment allume par 0 | ||
15 | -- false => segment allume par 1 | ||
16 | --------------------------------------------------- | ||
17 | -- Entrees/sorties | ||
18 | --------------------------------------------------- | ||
19 | -- hexa : entree code hexadacimal (4 bits) | ||
20 | -- abcdefg : sortie 7 segments | ||
21 | -- a : segment horizontal superieur | ||
22 | -- a est le MSB de abcdefg | ||
23 | -- b : segment vertical superieur droit | ||
24 | -- c : segment vertical inferieur droit | ||
25 | -- d : segment horizontal inferieur | ||
26 | -- e : segment vertical indefieur gauche | ||
27 | -- f : segment vertical superieur gauche | ||
28 | -- g : segment horizontal milieu | ||
29 | --------------------------------------------------- | ||
30 | |||
31 | entity seven_segment_decoder is | ||
32 | generic (active_low : boolean := true); | ||
33 | port (hexa : in std_logic_vector(3 downto 0); | ||
34 | hex : out std_logic_vector(6 downto 0)); | ||
35 | end ; | ||
36 | |||
37 | |||
38 | architecture RTL of seven_segment_decoder is | ||
39 | signal segments : std_logic_vector(hex'range); | ||
40 | signal abcdefg : std_logic_vector(hex'range); | ||
41 | begin | ||
42 | abcdefg <= segments when active_low else not segments; | ||
43 | process(abcdefg) is | ||
44 | begin | ||
45 | for i in hex'range loop | ||
46 | hex(i) <= abcdefg(hex'length-1-i); | ||
47 | end loop; | ||
48 | end process; | ||
49 | |||
50 | process(hexa) | ||
51 | begin | ||
52 | case hexa is | ||
53 | when "0000" => segments <= "0000001"; -- 0 | ||
54 | when "0001" => segments <= "1001111"; -- 1 | ||
55 | when "0010" => segments <= "0010010"; -- 2 | ||
56 | when "0011" => segments <= "0000110"; -- 3 | ||
57 | when "0100" => segments <= "1001100"; -- 4 | ||
58 | when "0101" => segments <= "0100100"; -- 5 | ||
59 | when "0110" => segments <= "0100000"; -- 6 | ||
60 | when "0111" => segments <= "0001111"; -- 7 | ||
61 | when "1000" => segments <= "0000000"; -- 8 | ||
62 | when "1001" => segments <= "0000100"; -- 9 | ||
63 | when "1010" => segments <= "0001000"; -- A | ||
64 | when "1011" => segments <= "1100000"; -- B | ||
65 | when "1100" => segments <= "0110001"; -- C | ||
66 | when "1101" => segments <= "1000010"; -- D | ||
67 | when "1110" => segments <= "0110000"; -- E | ||
68 | when "1111" => segments <= "0111000"; -- F | ||
69 | when others => segments <= "1111111"; | ||
70 | end case; | ||
71 | end process; | ||
72 | end ; | ||