FPGA/pwm/lpm_mux0.cmp


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic 
--functions, and any output files from any of the foregoing 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Altera Program License 
--Subscription Agreement, Altera MegaCore Function License 
--Agreement, or other applicable license agreement, including, 
--without limitation, that your use is for the sole purpose of 
--programming logic devices manufactured by Altera and sold by 
--Altera or its authorized distributors.  Please refer to the 
--applicable agreement for further details.


component lpm_mux0
	PORT
	(
		data0x		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		data1x		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		data2x		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		data3x		: IN STD_LOGIC_VECTOR (22 DOWNTO 0);
		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (22 DOWNTO 0)
	);
end component;