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path: root/FPGA/vhdl/greybox_tmp/cbx_args.txt
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LPM_AVALUE=000000000001
LPM_DIRECTION=LEFT
LPM_TYPE=LPM_SHIFTREG
LPM_WIDTH=12
DEVICE_FAMILY="Cyclone II"
aclr
aset
clock
enable
shiftin
q
shiftout