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authorPacien TRAN-GIRARD2014-04-11 19:29:53 +0200
committerPacien TRAN-GIRARD2014-04-11 19:29:53 +0200
commit12bbdb42cdcf5e6e39832d75fbbd31e3781d550a (patch)
tree21d9d8fdb7a949c8050de38c237386d0066ca146
downloadfpga-home-automation-12bbdb42cdcf5e6e39832d75fbbd31e3781d550a.tar.gz
Import fichiers projet Quartus
Diffstat
-rw-r--r--FPGA/vhdl/clock_divider.vhd57
-rw-r--r--FPGA/vhdl/codec_config.vhd92
-rw-r--r--FPGA/vhdl/codec_dac.vhd110
-rw-r--r--FPGA/vhdl/dds_sinus.vhd101
-rw-r--r--FPGA/vhdl/i2c_master.vhd255
-rw-r--r--FPGA/vhdl/lcd.vhd89
-rw-r--r--FPGA/vhdl/lcd_controller.vhd363
-rw-r--r--FPGA/vhdl/lcd_message.vhd158
-rw-r--r--FPGA/vhdl/message.vhd67
-rw-r--r--FPGA/vhdl/rom_sinus.vhd75
-rw-r--r--FPGA/vhdl/seven_segment_decoder.vhd72
11 files changed, 1439 insertions, 0 deletions
diff --git a/FPGA/vhdl/clock_divider.vhd b/FPGA/vhdl/clock_divider.vhd
new file mode 100644
index 0000000..3a061bb
--- /dev/null
+++ b/FPGA/vhdl/clock_divider.vhd
@@ -0,0 +1,57 @@
1------------------------------------------------------
2-- Clock Divider
3------------------------------------------------------
4-- Creation : A. Exertier, 2005
5------------------------------------------------------
6
7library ieee;
8use ieee.std_logic_1164.all;
9
10------------------------------------------------------
11-- PARAMETRES GENERIQUES
12------------------------------------------------------
13-- board_frequency : frequency of the FPGA
14-- user_frequency : desired frequency
15------------------------------------------------------
16-- INPUTS
17------------------------------------------------------
18-- clk : main clock
19-- resetn : asynchronous active low reset
20------------------------------------------------------
21-- OUTPUT
22------------------------------------------------------
23-- en_user : signal at user_frequency
24-- set to 1 only 1 main clock cycle
25------------------------------------------------------
26
27
28entity clock_divider is
29 generic(
30 board_frequency : real :=50_000_000.0; -- 50 MHz
31 user_frequency : real :=4.0); -- 4 Hz
32 Port (
33 clk : in std_logic;
34 resetn : in std_logic; -- active low
35 en_user : out std_logic);
36end clock_divider;
37
38architecture RTL of clock_divider is
39 constant max : natural := integer(board_frequency/user_frequency);
40begin
41 process(clk,resetn)
42 variable counter : natural range 0 to max-1;
43 begin
44 if resetn='0' then
45 counter := 0;
46 en_user <= '0';
47 elsif rising_edge(clk) then
48 if counter = max-1 then
49 counter := 0;
50 en_user <= '1';
51 else
52 counter := counter+1;
53 en_user <= '0';
54 end if;
55 end if;
56 end process;
57end RTL;
diff --git a/FPGA/vhdl/codec_config.vhd b/FPGA/vhdl/codec_config.vhd
new file mode 100644
index 0000000..2ae71f8
--- /dev/null
+++ b/FPGA/vhdl/codec_config.vhd
@@ -0,0 +1,92 @@
1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4
5entity codec_config is
6 generic (
7 system_frequency : real := 50.0E6; -- 50 MHz
8 i2c_rate : real := 20.0E3 -- 20 kHz
9 );
10 port (
11 clk : in std_logic;
12 resetn : in std_logic;
13 end_config : out std_logic;
14 i2c_scl : out std_logic;
15 i2c_sda : inout std_logic
16 );
17end entity;
18
19architecture rtl of codec_config is
20 type t_config is array(natural range 0 to 10) of std_logic_vector(23 downto 0);
21 constant config_data : t_config :=
22 (X"34001A",
23 X"34021A",
24 X"34047B",
25 X"34067B",
26 X"3408F8",
27 X"340A06",
28 X"340C00",
29 X"340E01",
30 X"341002",
31 X"341201",
32 X"000000"
33 );
34 type state is (init, config, finished);
35 signal i2c_data : std_logic_vector(23 downto 0);
36 signal i2c_go : std_logic;
37 signal i2c_ack : std_logic;
38 signal i2c_ready : std_logic;
39 signal ctr_data : natural range 0 to 10;
40 signal current_state : state;
41
42begin
43
44 i2c_data <= config_data(ctr_data);
45
46 process(resetn, clk) is
47 begin
48 if resetn = '0' then
49 ctr_data <= 0;
50 current_state <= init;
51 i2c_go <= '0';
52 end_config <= '0';
53 elsif rising_edge(clk) then
54 case current_state is
55 when init => i2c_go <= '1';
56 if i2c_ready = '0' then
57 current_state <= config;
58 ctr_data <= ctr_data+1;
59 end if;
60
61 when config => i2c_go <= '0';
62 if i2c_ready = '1' then
63 if ctr_data<10 then
64 current_state <= init;
65 else
66 current_state <= finished;
67 end if;
68 end if;
69 when finished => end_config <= '1';
70 i2c_go <= '0';
71 end case;
72
73 end if;
74 end process;
75
76
77 i2c_ctrl : entity work.i2C_master
78 generic map (
79 system_frequency => system_frequency,
80 i2c_rate => i2c_rate
81 )
82 port map (
83 clk => clk,
84 resetn => resetn,
85 go => i2c_go,
86 ready => i2c_ready,
87 data_in => i2c_data,
88 i2c_scl => i2c_scl,
89 i2c_sda => i2c_sda,
90 ack => i2c_ack
91 );
92end architecture; \ No newline at end of file
diff --git a/FPGA/vhdl/codec_dac.vhd b/FPGA/vhdl/codec_dac.vhd
new file mode 100644
index 0000000..0cfd858
--- /dev/null
+++ b/FPGA/vhdl/codec_dac.vhd
@@ -0,0 +1,110 @@
1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4
5entity codec_dac is
6 generic (
7 system_frequency : real := 50.0E6; -- 50 MHz
8 sample_rate : real := 48.0E3; -- 48 kHz
9 data_width : positive := 16; -- 16 bits
10 channel_num : positive := 2 -- dual channel
11 );
12 port (
13 clk : in std_logic; --
14 resetn : in std_logic; --
15 go : in std_logic;
16 data_in : in std_logic_vector(data_width-1 downto 0);
17 -- codec
18 tempo_dac : out std_logic;
19 end_dac : out std_logic;
20 codec_dac_bclk : out std_logic; -- B4
21 codec_dac_data : out std_logic; -- A4
22 codec_dac_lrck : out std_logic -- C6
23 );
24end entity;
25architecture rtl of codec_dac is
26 constant mod_bclk : positive := integer(system_frequency/(2.0*sample_rate*real(data_width)*real(channel_num)));
27 constant mod_lrck : positive := data_width*channel_num/2;
28 type state is (wait_for_go, tx);
29 signal current_state : state;
30 signal next_state : state;
31 signal ctr_bclk : natural range 0 to mod_bclk-1;
32 signal ctr_lrck : natural range 0 to mod_lrck-1;
33 signal reg_data : std_logic_vector(data_in'range);
34 signal cmd_data : std_logic_vector(1 downto 0);
35 signal bclk : std_logic;
36 signal lrck : std_logic;
37 signal end_bit : std_logic;
38begin
39 codec_dac_bclk <= bclk;
40 codec_dac_lrck <= lrck;
41 codec_dac_data <= reg_data(reg_data'low);
42 tempo_dac <= end_bit;
43 end_bit <= '0' when (ctr_bclk< mod_bclk-1) or bclk='0'
44 else '1';
45 -- registers and counters
46 process(clk, resetn) is
47 begin
48 if resetn ='0' then
49 bclk <= '0';
50 lrck <= '0';
51 reg_data <= (others => '0');
52 ctr_bclk <= 0;
53 ctr_lrck <= 0;
54 current_state <= wait_for_go;
55 elsif rising_edge(clk) then
56 current_state <= next_state;
57 if ctr_bclk< mod_bclk-1 then
58 ctr_bclk <= ctr_bclk+1;
59 else
60 ctr_bclk <= 0;