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author | Pacien TRAN-GIRARD | 2014-06-15 15:28:10 +0200 |
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committer | Pacien TRAN-GIRARD | 2014-06-15 15:28:10 +0200 |
commit | 4762ef9b7238f67d065775b752ebf51289c1f437 (patch) | |
tree | fb88da863e1bbc068d8258b285663013233ebe7b /FPGA/top/codec_clock.qsf | |
parent | fdd5c7e084529b2a09bed21aef44eb56e82075dc (diff) | |
download | fpga-home-automation-4762ef9b7238f67d065775b752ebf51289c1f437.tar.gz |
Clean project
Diffstat (limited to 'FPGA/top/codec_clock.qsf')
-rw-r--r-- | FPGA/top/codec_clock.qsf | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/FPGA/top/codec_clock.qsf b/FPGA/top/codec_clock.qsf deleted file mode 100644 index c11cd5a..0000000 --- a/FPGA/top/codec_clock.qsf +++ /dev/null | |||
@@ -1,78 +0,0 @@ | |||
1 | # -------------------------------------------------------------------------- # | ||
2 | # | ||
3 | # Copyright (C) 1991-2013 Altera Corporation | ||
4 | # Your use of Altera Corporation's design tools, logic functions | ||
5 | # and other software and tools, and its AMPP partner logic | ||
6 | # functions, and any output files from any of the foregoing | ||
7 | # (including device programming or simulation files), and any | ||
8 | # associated documentation or information are expressly subject | ||
9 | # to the terms and conditions of the Altera Program License | ||
10 | # Subscription Agreement, Altera MegaCore Function License | ||
11 | # Agreement, or other applicable license agreement, including, | ||
12 | # without limitation, that your use is for the sole purpose of | ||
13 | # programming logic devices manufactured by Altera and sold by | ||
14 | # Altera or its authorized distributors. Please refer to the | ||
15 | # applicable agreement for further details. | ||
16 | # | ||
17 | # -------------------------------------------------------------------------- # | ||
18 | # | ||
19 | # Quartus II 32-bit | ||
20 | # Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition | ||
21 | # Date created = 15:18:56 mai 26, 2014 | ||
22 | # | ||
23 | # -------------------------------------------------------------------------- # | ||
24 | # | ||
25 | # Notes: | ||
26 | # | ||
27 | # 1) The default values for assignments are stored in the file: | ||
28 | # codec_clock_assignment_defaults.qdf | ||
29 | # If this file doesn't exist, see file: | ||
30 | # assignment_defaults.qdf | ||
31 | # | ||
32 | # 2) Altera recommends that you do not modify this file. This | ||
33 | # file is updated automatically by the Quartus II software | ||
34 | # and any changes you make may be lost or overwritten. | ||
35 | # | ||
36 | # -------------------------------------------------------------------------- # | ||
37 | |||
38 | |||
39 | set_global_assignment -name FAMILY "Cyclone II" | ||
40 | set_global_assignment -name DEVICE EP2C35F672C6 | ||
41 | set_global_assignment -name TOP_LEVEL_ENTITY codec_clock | ||
42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" | ||
43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:18:56 MAI 26, 2014" | ||
44 | set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" | ||
45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files | ||
46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 | ||
47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 | ||
48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 | ||
49 | set_global_assignment -name USE_CONFIGURATION_DEVICE ON | ||
50 | set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" | ||
51 | set_global_assignment -name VHDL_FILE ../vhdl/clock_divider.vhd | ||
52 | set_global_assignment -name BDF_FILE codec_clock.bdf | ||
53 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top | ||
54 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top | ||
55 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top | ||
56 | set_location_assignment PIN_N25 -to alarm_user | ||
57 | set_location_assignment PIN_P25 -to speed_user[0] | ||
58 | set_location_assignment PIN_AE14 -to speed_user[1] | ||
59 | set_location_assignment PIN_N26 -to fan_auto_user | ||
60 | set_location_assignment PIN_AE23 -to alarm | ||
61 | set_location_assignment PIN_AF23 -to fan_auto | ||
62 | set_location_assignment PIN_AB21 -to speed[0] | ||
63 | set_location_assignment PIN_AC22 -to speed[1] | ||
64 | set_location_assignment PIN_N2 -to clk | ||
65 | set_location_assignment PIN_G26 -to resetn | ||
66 | set_location_assignment PIN_M23 -to hot | ||
67 | set_location_assignment PIN_K26 -to fan | ||
68 | set_location_assignment PIN_B4 -to aud_bclk | ||
69 | set_location_assignment PIN_A4 -to aud_dacdat | ||
70 | set_location_assignment PIN_C6 -to aud_daclrck | ||
71 | set_location_assignment PIN_A5 -to aud_xck | ||
72 | set_location_assignment PIN_A6 -to i2c_sclk | ||
73 | set_location_assignment PIN_B6 -to i2c_sdat | ||
74 | set_location_assignment PIN_M20 -to sound_high_level | ||
75 | set_location_assignment PIN_Y18 -to led_fan | ||
76 | set_location_assignment PIN_AE22 -to end_config | ||
77 | set_location_assignment PIN_M25 -to xti_mclk | ||
78 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file | ||